
BCRTM-43
MCLKD2
ADDRESS
DATA
AEN
BURST
DMA GRANT RECOGNIZED ON THIS EDGE
THMC1+10
MCLK+20
40
SYMBOL
t
SHL16
t
PHL1
t
PHL21
t
PZL16
t
HLH2
t
PHL3
t
PW21
t
OOZL1
t
PHL4
t
PHL4
MIN
-5
10
MAX
+5
10
UNITS
ns
ns
0
THMC1-10
MCLK-20
MCLK
-10
ns
ns
ns
ns
ns
ns
ns
s
μ
s
0
0
0
2x-2MCLK
μ
45
4xMCLK
6xMCLK
10
3.5 (1.9)
1.9 (0.8)
MCLK = period of the memory clock cycle.
BURST signal is for multiple-word DMA accesses.
THMC1 is equivalent to the positive phase of MCLK (see figure 27).
DMAR
DMAG
DMACK
TSCTL
MEMCSO
t
SHL1
t
PW2
t
OOZL1
t
PHL4
t
PHL1
t
PHL2
t
PZL1
t
PHL3
RWR/RRD
2
DMACK
↓
to DMAR High Impedance RAD
NON-RAD
DMAG
↓
to DMACK
↓
DMAG
↓
to TSCTL
↓
TSCTL
↓
to ADDRESS valid RAD
NON-RAD
RWR/RRD
↑
to DMACK
↑
TSCTL
↓
to RWR/RRD
↓
DMAG
↓
to DMAG
↑
DMAR
↓
to BURST
↑
DMAR
↓
to DMAG
↓
5
DMAR
↓
to DMAG
↓
4
Notes:
1. Guaranteed by test.
2. See figures 27 & 28 for detailed DMA read and write timing.
3.
DMAG
must be asserted at least 45ns prior to the rising edge of MCLKD2 in order to be recognized for the next MCLKD2 cycle.
If
DMAG
is not asserted at least 45ns prior to the rising edge of MCLKD2,
DMAG
is not recognized until the following MCL
KD2 cycle.
4. Provided MCLK = 12MHz. Number in parentheses indicates the longest
DMAR
↓
to
DMAG
↓
allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
5. Provided MCLK = 6MHz. Number in parentheses indicates the longest
DMAR
↓
DMAG
↓
allowed during worst-case bus switching conditions
in order to meet MIL-STD-1553B RT Response Time. The number not in parentheses applies to all other circumstances.
6. Tested only at initial qualification, and after any design or process changes which may affect this characteristic.
t
HLH2
Figure 26. BURST DMA Timing