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參數(shù)資料
| 型號： | A60Q30-2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 保險絲 |
| 英文描述： | SEMICONDUCTOR PROTECTION FUSES |
| 中文描述： | 半導(dǎo)體保護(hù)保險絲 |
| 文件頁數(shù)： | 37/61頁 |
| 文件大?。?/td> | 2024K |
| 代理商： | A60Q30-2 |
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BCRTM-37
The interrupt structure also uses three BCRTM- driven output
signals to indicate when an interrupt event occurs:
STDINTL
Standard Interrupt Level. This signal is
asserted when one or more of the events
enabled in the Standard Interrupt Enable
Register occurs. Clear the signal by resetting
the Standard Interrupt bit in the High-Priority
Interrupt Status/Reset Register.
STDINTP
Standard Interrupt Pulse. This signal is
pulsed for each occurrence of an event
enabled in the Standard Interrupt
Enable Register.
HPINT
High-Priority Interrupt. This signal is
asserted for each occurrence of an event
enabled in the High-Priority Interrupt/Enable
Register. Writing to the corresponding bit in
the High-Priority Status/Reset Register
resets it.
Interrupt Status Word Definition
All bits in the Interrupt Status Word are active high and have the following functions:
Bit
Number
Description
BIT 15
Interrupt Status Word Accessed. The BCRT always sets this bit during the DMA Write of the Interrupt.
Status Word. If the CPU resets this bit after reading the Interrupt Status Word, the bit can help the CPU determine
which entries have been acknowledged.
No Response Time-Out (Message Error condition). Further defines the Message Error condition to indicate that a
Response Time-Out condition has occurred.
(RT) Message Error (ME). Indicates the ME bit was set in the 1553 status word response.
BITs 12-8 Reserved.
BIT 7
(RT) Subaddress Event or Mode Code with Data Word Interrupt. Indicates a descriptor control word has been
accessed with either an Interrupt Upon Valid Command Received bit set or an Interrupt when Index=0 bit set (and
the Index is decremented to 0).
BIT 6
(RT) Mode Code without Data Word Interrupt. Indicates a mode code has occurred with an Interrupt When
Addressed interrupt enabled.
BIT 5
(RT) Illegal Broadcast Command. Applies to receive commands only. This bit indicates that a received command,
due to an illegal mode code or subaddress field, has been received in the broadcast mode. This does not include
invalid commands.
BIT 4
(RT) Illegal Command. This indicates that an illegal command has occurred due to an illegal mode code or
subaddress and T/R field. This does not include invalid commands.
BIT 3
(BC) Polling Comparison Match. Indicates a polling comparison interrupt.
BIT 2
(BC) Retry Fail. Indicates all the programmed retries have failed.
BIT 1
(BC, RT) Message Error. Indicates a Message Error has occurred.
BIT 0
(BC) Interrupt and Continue. This corresponds to the interrupt and continue function described in the Command
Block.
BIT 14
BIT 13
Figure 21. Interrupt Log List
ENTRY #3
ENTRY #2
ENTRY #1
TAIL POINTER
COMMAND BLOCK
POINTER
CODE DESCRIPTOR
POINTER
INTERRUPT STATUS
WORD
POINTER REGISTER
INTERRUPT LOG LIST
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| A60Q15-2 | SEMICONDUCTOR PROTECTION FUSES |
| A60Q20-2 | SEMICONDUCTOR PROTECTION FUSES |
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