
BCRTM-1
UT1553 BCRTM
F
EATURES
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Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
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MIL-STD-1773 compatible
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Multiple message processing capability in BC
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Time tagging and message logging in RT and M modes
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Automatic polling and intermessage delay in
BC mode
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Programmable interrupt scheme and internally
generated interrupt history list
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Register-oriented architecture to enhance
programmability
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DMA memory interface with 64K addressability
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Internal self-test
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Radiation-hardened option available for 84-lead
flatpack package only
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Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
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Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
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Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
16
16
16
CONTROL
DMA/CPU
RT/MONITOR
MESSAGE
BC PROTOCOL
&
IHANDLER
SION
CONVER-
SION
CONVER-
MODULE
DECODER
CDUAL
BUS
TRANSFER
LOGIC
ADDRESS
16
TIMEOUT
TIMERON
CLOCK &
RESET
LOGIC
12MHz
MASTER
RESET
GENERATOR
ADDRESS
16
1553
DATA
CHANNEL
B
HIGH-PRIORITY
INTERRUPT ENABLE
RT ADDRESS
STANDARD INTERRUPT
ENABLE
HIGH-PRIORITY
INTERRUPT STATUS
INTERRUPT LOG
LIST POINTER
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC (or M) BLOCK/
RT DESCRIPTOR SPACE
STATUS
CONTROL
REGISTERS
DATA
16
BUILT-
IN-
TEST
16
16
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
1553
DATA
CHANNEL
A
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
BUILT-IN-TEST
START COMMAND
RESET COMMAND
MSELECT (16-31)
Figure 1. BCRTM Block Diagram
RT TIMER
RESET COMMAND