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參數(shù)資料
| 型號： | A60Q30-2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 保險絲 |
| 英文描述： | SEMICONDUCTOR PROTECTION FUSES |
| 中文描述： | 半導(dǎo)體保護(hù)保險絲 |
| 文件頁數(shù)： | 16/61頁 |
| 文件大?。?/td> | 2024K |
| 代理商： | A60Q30-2 |
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BCRTM-16
#10 Remote Terminal Address Register
This register sets the Remote Terminal Address via software. The Change Lock-Out Enable feature, when set, prevents the
Remote Terminal Address or the BCRTM Mode Selection from changing.
Bit
Number
Description
BIT 15
BIT 14
BIT 13
(RT) Instrumentation. Setting this bit sets the RT status word Instrumentation bit.
(RT) Busy. Setting this bit sets the RT status word Busy bit. It does not inhibit data transfers to the subsystem.
(RT) Subsystem Fail. Setting this bit sets the RT status word Subsystem Flag bit. In the RT mode, the Subsystem
Fail is also logged into the Message Status Word.
(RT) Dynamic Bus Control Acceptance. Setting this bit sets the RT status word Dynamic Bus Control
Acceptance bit when the BCRTM receives the Dynamic Bus Control Mode Code from the currently active Bus
Controller. Host intervention is required for the BCRTM to take over as the active Bus Controller.
(RT) Terminal Flag. Setting this bit sets the RT status word Terminal Flag bit; the Terminal Flag bit in the RT
status word is also internally set if the BIT fails.
(RT) Service Request. Setting this bit sets the RT status word Service Request bit.
(RT) Busy Mode Enable. Setting this bit sets the RT status word Busy bit and inhibits all data transfers to the
subsystem.
BC/RT Mode Select. This bit’s state reflects the external pin BCRTSEL. It does not necessarily reflect the state
of the chip, since the BC/RT Mode Select is software-programmable via bit 10 of Register 0. This bit is
read-only.
Change Lock-Out. This bit’s state reflects the external pin LOCK. When set, this bit indicates that changes to the
RT address or the BC/RT Mode Select are not allowed using internal registers. This bit is read-only.
Remote Terminal Address Parity Error. This bit indicates a Remote Terminal Address Parity Error. It appears
after the Remote Terminal Address is latched if a parity error exists.
Remote Terminal Address Parity. This is an odd parity input bit used with the Remote Terminal Address. It
ensures accurate recognition of the Remote Terminal Address.
Remote Terminal Address (Bit 0 is the LSB). This reflects the RTA4-0 inputs at Master Reset. Modify the
Remote Terminal Address by writing to these bits.
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BITs 4-0
#11 BIT Start Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates the internal BIT routine, which lasts 100
μ
s. Verify
using the BIT-in-Progress bit in the Status Register. A programmed reset (write to Register 12) must precede a write to this
register to initiate the internal BIT.A failure of the BIT will be indicated in Register 4 and the BCRTF pin.
The BCRTM’s self-test performs an internal wrap-around test between its Manchester encoder and its two Manchester decoders.
If the BCRTM detects a failure on either the primary or the secondary channel, it flags this failure by setting bit 14 of Register
4 (BIT Word Register) for Channel A and/or bit 15 for Channel B. When in the Remote Terminal mode, while the BCRTM is
performing its self-test, it ignores any commands on the 1553 bus until it has completed the self-test.
#12 Programmed Reset Register (Write Only)
Any write (i.e., data = don’t care) to this register’s address location initiates a reset sequence of the encoder/decoder and
protocol sections of the BCRTM which lasts less than 1 microsecond. This is identical to the reset used for the Reset Remote
Terminal Mode Code except that command processing halts. For a total reset (i.e., including registers), see the MRST signal
description.
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| A60Q8-2 | 制造商:Ferraz Shawmut 功能描述: |
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