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參數(shù)資料
| 型號： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A16450 |
Altera Corporation
73
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 6
lists the word length associated with bits 0 and 1.
Table 5. Line Control Register Format
Bit
Description
1..0
Word length control. Sets the length of the word associated with each transmitted or received word.
See
Table 6
.
Stop control bit. Controls the number of stop bits generated by the transmitter section. The receiver
circuitry checks for the first stop bit only, regardless of the state of bit 2. See
Table 7
.
Parity enable. When set to a logic high, parity generation in the transmitter section and parity
checking in the receiver section are enabled. The parity bit is inserted between the last word bit and
the first stop bit.
Parity even/odd. When set to a logic high, even parity is enabled; when set to a logic low, odd parity
is enabled.
Stick parity. Forces the parity bit to a known value. If parity is enabled and even parity is selected, the
transmitter section will transmit the parity bit as a logic low. Then, the receiver section checks that the
incoming parity bit is set to logic low.
Break control. When set, bit 6 forces the
a16450
to transmit a break condition. The
sout
output is
forced to a logic low state for longer than one full word transmission. Disable the break by clearing
bit 6, which causes
sout
to return to a logic high. The
sout
output is set to a logic high upon master
reset.
Divisor register access bit (
drab
). This bit must be set high to access the divisor registers. A low
enables access to the receiver buffer and transmitter holding registers.
2
3
4
5
6
7
Table 6. Word Length Control Format
Bit 0
Bit 1
Word Length
0
1
0
1
0
0
1
1
5 bits
6 bits
7 bits
8 bits
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