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參數(shù)資料
| 型號： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A16450 |
76
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Scratchpad Register
The scratchpad register is a general-purpose register provided for the
convenience of the user.
Table 10. Modem Status Register Format
Bit
Signal
Description
0
dcts
Delta clear to send. Indicates that the
ncts
input has changed state since the
processor last read the modem status register. When bit 0 is set to a logic high, a
modem status interrupt is generated.
Delta data set ready. Indicates that the
ndsr
input has changed since the processor
last read the modem status register. When bit 1 is set to a logic high, a modem status
interrupt is generated.
Trailing edge ring indicator. Indicates that a trailing (0 to 1) edge has occurred on the
nri
input since the processor last read the modem status register. When bit 2 is set
to a logic high, a modem status interrupt is generated.
Delta data carrier detect. Indicates that the
ndcd
input has changed state since the
processor last read the modem status register. When bit 3 is set to a logic high, a
modem status interrupt is generated.
Clear to send. This bit is the complement of the
ncts
input.
Data set ready. This bit is the complement of the
ndsr
input.
Ring indicator. This bit is the complement of the
nri
input.
Data carrier detect. This bit is the complement of the
ndcd
input.
1
ddsr
2
teri
3
ddcd
4
5
6
7
cts
dsr
ri
dcd
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