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參數(shù)資料
| 型號(hào)： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 281K |
| 代理商： | A16450 |
Altera Corporation
71
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Interrupt Identification Register
The
a16450
has a priority encoding scheme for its four interrupt sources.
Table 4
shows the encoding scheme for each of the interrupts, their
priority, and the reset mechanism for each interrupt source. When set to a
logic low, bit 0 indicates that an interrupt is pending. Bits 1 and 2 indicate
the interrupt priority, and bits 3 through 7 are read-only bits that are
always set to a logic low.
Clearing an interrupt source does not affect any lower priority interrupts
that might be pending. When the interrupt identification register is
accessed, the highest priority interrupt at the beginning of the access is
recorded in the register. Other interrupts, including those of higher
priority, are recorded but are not recognized until the current register
access is complete.
Table 3. Interrupt Enable Register Format
Bit
Signal
Description
0
rda
Received data available. When set to a logic high, bit 0 enables
interrupts when receive data is loaded in the receiver buffer
register.
Transmitter holding register empty. When set to a logic high, bit 1
enables interrupts when the transmitter holding register is empty.
Receiver line status. When set to a logic high, bit 2 enables
interrupts when the receiver line status register changes state.
Modem status. When set to a logic high, bit 3 enables interrupts
when the modem status register changes state.
Read-only bits that are always set to a logic low.
1
thre
2
rls
3
ms
7..4
–
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