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參數(shù)資料
| 型號： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A16450 |
66
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 1
describes the input and output ports of the
a16450
.
Table 1. a16450 Ports (Part 1 of 2)
Name
Type
Polarity
Description
nads
Input
Low
Address strobe. Enable signal to the address input receiver. The positive
edge of
nads
latches the register address bus into the address input
register.
Clock. Provides the master timing reference to the
Chip select 0. The
a16450
is selected when
asserted, which permits read and write transactions to internal registers.
Chip select 1. The
a16450
is selected when
asserted, which permits read and write transactions to internal registers.
Chip select 2. The
a16450
is selected when
asserted, which permits read and write transactions to internal registers.
Clear to send. Indicates that the modem is ready to exchange data. A
change in input state from low to high is recorded in bit 0 of the modem
status register. If the modem status interrupt is enabled when
changes state, an interrupt is generated. This input’s complement is
recorded in bit 4 of the modem status register.
Data carrier detect. Indicates that the modem or data set detected a data
carrier. A change in input state is recorded in bit 3 of the modem status
register. If the modem status interrupt is enabled when
state, an interrupt is generated. This input’s complement is recorded in bit 7
of the modem status register.
Data set ready. Indicates that the modem or data set is ready to establish
the communications link with the
a16450
recorded in bit 1 of the modem status register. If the modem status interrupt
is enabled when
ndsr
changes state, an interrupt is generated. This input’s
complement is recorded in bit 5 of the modem status register.
Master reset. Clears all registers (except the receiver buffer, transmitter
holding, and divisor registers) to their initial state. Resets control logic to
initial state.
Receiver clock. Operates at 16 times the baud rate clock.
Read control. When
rd
or
nrd
is asserted and the
read transactions from internal registers are possible.
Read control. When
rd
or
nrd
is asserted and the
read transactions from internal registers are possible.
Ring indicator. Indicates that the modem or data set detected the ring
signal. A change in input state is recorded in bit 2 of the modem status
register. If the modem status interrupt is enabled when
an interrupt is generated. This input’s complement is recorded in bit 6 of the
modem status register.
clk
Input
Input
–
a16450
, and
.
cs0
High
cs0
,
cs1
ncs2
are
cs1
Input
High
cs0
,
cs1
, and
ncs2
are
ncs2
Input
Low
cs0
,
cs1
, and
ncs2
are
ncts
Input
Low
ncts
ndcd
Input
Low
ndcd
changes
ndsr
Input
Low
. A change in input state is
mr
Input
High
rclk
Input
Input
–
rd
High
a16450
is selected,
nrd
Input
Low
a16450
is selected,
nri
Input
Low
nri
changes state,
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