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參數(shù)資料
| 型號： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A16450 |
74
Altera Corporation
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Table 7
lists the number of stop bits and word length associated with bit 2.
Note:
(1)
The X indicates “don’t care.”
Modem Control Register
The modem control register controls the modem interface outputs.
Table 8
describes the modem control register format.
Line Status Register
The line status register enables the host processor to examine data
transfers.
Table 9
describes the line status register format.
Table 7. Stop Bit Control Format
Bit 2
Word Length
Note (1)
Number of Stop Bits
0
1
1
1
1
X
1
1.5
2
2
2
5 bits
6 bits
7 bits
8 bits
Table 8. Modem Control Register Format
Bit
Signal
Description
0
1
2
3
4
dtr
Data terminal ready. The user can program the
dtr
bit to control the
ndtr
output.
Request to send. The user can program the
rts
bit to control the
nrts
output.
Output 1. The user can program the
out1
bit to control the
nout1
output.
Output 2. The user can program the
out2
bit to control the
nout2
output.
Enable loopback. When high, bit 4 causes the following:
I
The
sout
output is set to a logic high.
I
The
sin
input is disconnected (i.e., ignored).
I
The output of the transmitter shift register is internally connected (loopbacked) to the
receiver shift register input.
I
The modem control inputs are disconnected (i.e., ignored).
I
The modem control outputs are used internally in place of the modem control inputs.
Not used. These read-only bits are always set to a logic low.
rts
out1
out2
el
7..5
–
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