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參數(shù)資料
| 型號： | a16450 |
| 廠商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用異步接收/傳送器) |
| 中文描述： | 通用異步接收器/發(fā)送器（通用異步接收/傳送器） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 281K |
| 代理商： | A16450 |
Altera Corporation
75
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet
Modem Status Register
The modem status register enables the microprocessr to examine the
condition of the modem interface inputs.
Table 10
shows the modem
status register format.
Table 9. Line Status Register Format
Bit
Signal
Description
0
rdr
Receiver data ready. Indicates that an incoming word has been received and transferred to the
receiver buffer register. When bit 0 is set to a logic high, a receive data available interrupt is
generated. Bit 0 is cleared by reading the receiver buffer register.
Overrun error. Indicates that new data wrote over unread data in the receiver buffer register.
When bit 1 is set to a logic high, a receiver line status interrupt is generated. Bit 1 is cleared by
reading the line status register.
Parity error. Indicates that newly received data had incorrect parity. When bit 2 is set to a logic
high, a receiver line status interrupt is generated. Bit 2 is cleared by reading the line status
register.
Framing error. Indicates that newly received data had an invalid stop bit. When bit 3 is set to a
logic high, a receiver line status interrupt is generated. Bit 2 is cleared by reading the line status
register.
Break interrupt. Indicates that a break condition was detected on the serial input. A break
condition occurs when the serial data in (
sin
) is held at logic low for longer than one full word
transmission. When bit 4 is set to a logic high, a receiver line status interrupt is generated. Bit 4
is cleared by reading the line status register.
thre
Transmitter holding register empty. Indicates that the
a16450
is ready to accept a new data
word from the microprocessor for transmission. When bit 5 is set to a logic high, a transmitter
holding register empty interrupt is generated. Bit 5 is cleared by reading the interrupt ID register
or by writing to the transmitter holding register.
Transmitter empty. Indicates that the transmitter holding register and the transmitter shift
register are both empty.
–
Not used. This read-only bit is always set to a logic low.
1
oe
2
pe
3
fe
4
bi
5
6
tre
7
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