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參數(shù)資料
| 型號(hào)： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁(yè)數(shù)： | 41/90頁(yè) |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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32
Electrical Data
Chapter 7
AMD Athlon Processor Model 4 Data Sheet
23792I—June 2001
Preliminary Information
7.12
General AC and DC Characteristics
Table 13 shows the AMD Athlon Processor Model 4 AC and DC
ch aracte r i s t i c s of the Southbr i d ge , J TAG , tes t , and
miscellaneous pins.
Table 13. General AC and DC Characteristics
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
VIH
Input High Voltage
(VCC_CORE/2) +
200mV
VCC_CORE +
300mV
V1,2
VIL
Input Low Voltage
–300
350
mV
1,2
VOH
Output High Voltage
VCC_CORE –
400
VCC_CORE +
300
mV
VOL
Output Low Voltage
–300
400
mV
ILEAK_P
Tristate Leakage Pullup
VIN = VSS
(Ground)
–1mA
ILEAK_N
Tristate Leakage Pulldown
VIN = VCC_CORE
Nominal
600
A
IOH
Output High Current
–16
mA
3
IOL
Output Low Current
16
mA
3
TSU
Sync Input Setup Time
2.0
ns
4, 5
THD
Sync Input Hold Time
0.0
ps
4, 5
TDELAY
Output Delay with respect to RSTCLK
0.0
6.1
ns
5
TBIT
Input Time to Acquire
20.0
ns
7,8
TRPT
Input Time to Reacquire
40.0
ns
9-13
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
3. IOL and IOH are measured at VOL max and VOH min, respectively.
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to guarantee capture.
8. This value assumes RSTCLK frequency is 10ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, LowPower mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
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