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參數(shù)資料
| 型號(hào)： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁(yè)數(shù)： | 38/90頁(yè) |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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Chapter 7
Electrical Data
29
23792I—June 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
Table 10 shows the SYSCLK/SYSCLK# differential clock AC
characteristics of the AMD Athlon Processor Model 4. Figure 9
shows a sample waveform.
Figure 9. SYSCLK Waveform
Table 10. SYSCLK and SYSCLK# AC Characteristics
Symbol
Parameter Description
Min @
Max @
Units
Notes
Clock Frequency
100
133
100
133
MHz
Duty Cycle
30%
70%
t1
Period
10
7.5
ns
1, 2
t2
High Time
1.8
1.05
nS
t3
Low Time
1.8
1.05
ns
t4
Fall Time
2
ns
t5
Rise Time
2
ns
Period Stability
± 300
ps
Notes:
1. Circuitry driving the SYSCLK & SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow
the PLL to track the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load must be less than
500 kHz.
2. Circuitry driving the SYSCLK & SYSCLK# inputs can purposely alter the SYSCLK & SYSCLK# period (spread
spectrum clock generators). In no cases can the SYSCLK & SYSCLK# period violate the minimum specification
above. SYSCLK & SYSCLK# inputs can vary from 100% of the specified period to 99% of the specified period at
a maximum rate of 100 kHz.
t5
VCROSS
t2
t3
t4
t1
VThreshold-AC
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