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參數(shù)資料
| 型號： | A1400AMT3C |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | STAGGERED, CERAMIC, PGA-453 |
| 文件頁數(shù)： | 40/90頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | A1400AMT3C |
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Chapter 7
Electrical Data
31
23792I—June 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
The AC characteristics of the AMD Athlon system bus are
shown in Table 12 on page 31. The parameters are grouped
based on the source or destination of the signals involved.
Table 12. AMD Athlon System Bus AC Characteristics
Group
Symbol
Parameter
Min
Max
Units
Notes
All Signals
TRISE
Output Rise Slew Rate
1
3
V/ns
1
TFALL
Output Fall Slew Rate
1
3
V/ns
1
Fo
rw
ard
Cloc
ks
TSKEW-
SAMEEDGE
Output skew with respect to
the same clock edge
385
ps
2
TSKEW-
DIFFEDGE
Output skew with respect to a
different clock edge
770
ps
2
TSU
Input Data Setup Time
300
ps
3
THD
Input Data Hold Time
300
ps
3
CIN
Capacitance on input Clocks
4
12
pF
COUT
Capacitance on output Clocks
4
12
pF
Sy
nc
4
TVAL
RSTCLK to Output Valid
250
2000
ps
5
TSU
Setup to RSTCLK
500
ps
6
THD
Hold from RSTCLK
1000
ps
6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and
its forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and
its forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
PROCRDY, CONNECT, CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge
of RSTCLK.
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