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參數(shù)資料
| 型號： | 97SD3248RPMK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 758K |
| 代理商： | 97SD3248RPMK |
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97SD3248
M
em
o
ry
15
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
To [ACTV]: This command makes the other bank active. ( However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of t
RAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the operation is completed.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM then enters precharge mode.
To [ACTV]: This command makes other banks active. (However, an interval of t
RRD is required.) Attempting
to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of t
RRD is required.)
Attempting to make the currently active bank active result in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP]: After an auto-refresh cycle (after t
RC) the SDRAM automatically enters the IDLE state.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3248RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SG-1 | 制造商:EECO Switch 功能描述: |
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