參數(shù)資料
型號: 97SD3248RPMK
廠商: MAXWELL TECHNOLOGIES
元件分類: DRAM
英文描述: 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
封裝: STACK, QFP-132
文件頁數(shù): 31/40頁
文件大?。?/td> 758K
代理商: 97SD3248RPMK
97SD3248
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All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal
state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command
input is enabled from the next clock. For more details, refer to the “CKE Truth Table”.
Power-up sequence: The SDRAM should use the following sequence during power-up:
The CLK, CKE, CS, DQM and DQ pins stay low until power stabilizes.
The CLK pin is stable within 100ms after power stabilizes before the following initialization sequence.
The CKE and DQM is driven high between when power stabilizes and the initialization sequence.
This SDRAM has V
CC clamp diodes for CLK, CKE, CS, DQM and DQ pins. If these pins go high before
power up, the large current flows from these pins to V
CC through the diodes.
Initialization sequence: When 200ms or more has past after the power up sequence, all banks must be
precharged using the precharge command (PALL). After t
RP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. It is recommended that by
keeping DQM and CKE High, the output buffer becomes High-Z during initialization sequence, to avoid DQ
bus contention on a memory system formed with a number of devices.
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