- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25548 > 97SD3248RPMK (MAXWELL TECHNOLOGIES) 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 PDF資料下載
參數(shù)資料
| 型號： | 97SD3248RPMK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 758K |
| 代理商： | 97SD3248RPMK |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
97SD3248
M
em
o
ry
12
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
Function Truth Table
The following function table shows the operations that are performed when each command is issued in each
mode of the SDRAM.
The following table assumes that CKE is High.
CURRENT STATE
CS
RAS
CAS
WE
ADDRESS
COMMAND
OPERATION
Precharge
H
x
DESL
Enter IDLE after t
RP
L
H
x
NOP
Enter IDLE after t
RP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL1
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL1
L
H
BA, RA
ACTV
ILLEGAL1
L
H
L
BA, A10
PRE, PALL
NOP2
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
Idle
H
x
DESL
NOP
LH
H
x
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL3
L
H
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL3
L
H
BA, RA
ACTV
Bank and row active
L
H
L
BA, A10
PRE, PALL
NOP
L
H
x
REF, SELF
Refresh
L
MODE
MRS
Mode register set
Row active
H
x
DESL
NOP
LH
H
x
NOP
L
H
L
H
BA, CA, A10
READ/READ A
Begin read
L
H
L
BA, CA, A10
WRIT/WRIT A
Begin write
L
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank4
L
H
L
BA, A10
PRE, PALL
Precharge
L
H
x
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 97U870AKIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 97U870AH | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97U870AHIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97U870AKT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 97U870AHT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3248RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SG-1 | 制造商:EECO Switch 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。