參數(shù)資料
型號： 97SD3248RPMK
廠商： MAXWELL TECHNOLOGIES
元件分類： DRAM
英文描述： 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132
封裝： STACK, QFP-132
文件頁數(shù)： 38/40頁
文件大?。?/td> 758K
代理商： 97SD3248RPMK
97SD3248
M
em
o
ry
7
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
Pin Functions:
CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS 1-6 (INPUT PINS): When CS 1-6 are low, the command input cycle becomes valid. When CS 1-6 are High,
all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels.
A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-
charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1
(BS) is pre charged.
BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 97SD3248 is divided
into bank 0, bank 1, bank 2 and bank 3. The 97SD3248 contains 8192-row X 1024-column X 48-bit. If BA0
and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and
BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode,
clock suspend mode and self refresh mode1.
DQM 1-6 (INPUT PINS): DQM 1-6 control input/output buffers
Read operation: If DQM 1-6 are High, the output buffer becomes High-Z. If the DQM 1-6 are Low, the output
buffer becomes Low-Z. ( The latency of DQM 1-6 during reading is 2 clock cycles.)
Write operation: If DQM 1-6 are High, the previous data is held ( the new data is not written). If the DQM 1-6
areLow, the data is written. ( The latency of DQM 1-6 during writing is 0 clock cycles.)
DQ0 TO DQ47 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ47).
V
CC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output
buffer.)
V
SS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
1. Self refresh mode should only be used at temperatures below 70°C.
相關(guān)PDF資料
PDF描述
97U870AKIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
97U870AH 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AHIT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
97U870AKT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40
97U870AHT 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
97SD3248RPQE 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQH 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQI 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SD3248RPQK 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
97SG-1 制造商:EECO Switch 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*