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參數(shù)資料
| 型號： | 97SD3248RPMK |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 758K |
| 代理商： | 97SD3248RPMK |
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97SD3248
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35
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
DQM Control
The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and
the corresponding data is not output. However, internal reading operations continue. The latency of DQM
during reading is 2 clocks.
Writing: Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when
DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM
during writing is 0 clock.
Reading
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3248RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SG-1 | 制造商:EECO Switch 功能描述: |
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