參數(shù)資料
型號(hào)： 935269343557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT322-2, MS-022, QFP-160
文件頁數(shù)： 82/143頁
文件大?。?/td> 696K
代理商： 935269343557
2004 Aug 25
43
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
114
VF2
12
R
Video FIFO 2 underow/overow: this bit is set when the video FIFO 2
has an overow/underow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
VF1
11
R
Video FIFO 1 overow: this bit is set when the video FIFO 1 has an
overow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
AF2_in
10
R
Audio input FIFO 2 underow: this bit is set when the audio input
FIFO 2 has an underow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF2_out
9
R
Audio output FIFO 2 overow: this bit is set when the audio output
FIFO 2 has an overow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF1_in
8
R
Audio input FIFO 1 underow: this bit is set when the audio input
FIFO 1 has an underow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
AF1_out
7
R
Audio output FIFO 1 overow: this bit is set when the audio output
FIFO 1 has an overow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
6
reserved
VGT
5
R
Vertical Gate: this bit reects the vertical gate at the HPS output
LNQG
4
R
Line Qualier Gate: this bit reects the horizontal gate at the HPS
output
EC5S
3
R
Event Counter 5 Status: this bit is set when event counter 5 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
EC4S
2
R
Event Counter 4 Status: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
EC2S
1
R
Event Counter 2 Status: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
EC1S
0
R
Event Counter 1 Status: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
935269481115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269480115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269479115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269476115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269478115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
935269544557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3
935269987557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557
935270713557 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP
935270792551 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
935270792557 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*