參數(shù)資料
型號(hào)： 935269343557
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT322-2, MS-022, QFP-160
文件頁數(shù)： 11/143頁
文件大?。?/td> 696K
代理商： 935269343557
2004 Aug 25
108
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.4.2
Audio data path
Figure 39 illustrates the audio data path. An input
multiplexer selects serial data from one of four SD pins.
A1 can select SD0 and the common serial data pins SD1,
SD2 and SD3. A2 can select SD4 and the common serial
data pins SD1, SD2 and SD3. A serial-to-parallel converter
collects 8 bits to form a byte in a timeslot. At the end of the
time slot this byte can be stored into a Dword buffer, and/or
into the feedback buffer or can be thrown away. The first
byte that is latched, is placed into the first byte place of the
buffer, the second byte that is latched, is placed into the
second byte place, etc.
Big-endian and little-endian stuffing is supported. If bytes
are not latched into a certain buffer, the place pointer of the
corresponding buffer is not incremented. The write (fill)
pointer of the feedback buffer is reset to it’s initial position
with every start/restart of the super frame. Up to four bytes
of the input data stream can be placed in the intermediate
feedback buffer. They can be selected from the buffer to
provide data to the output.
The feedback buffer is also read and write accessible via
the PCI-bus. This allows reading of status information and
writing of control information at specific positions in the
audio frame. The write access is only possible when the
interface is inactive. The samples of the various real world
audio signal streams are byte or word interleaved in
system memory and PCI address space. It is the
responsibility of system/board designer and of
software/programmer to produce a reasonable sample
ordering, e.g. have a 16-bit sample on a word boundary
and not crossing a Dword boundary.
Fig.39 Audio data flow control in A1 and A2.
handbook, full pagewidth
MGG277
SD0
SD4
SD3
SD2
SD1
serial data lines
feedback buffer
status/control
information
via PCI
SERIAL-TO-
PARALLEL
PARALLEL-
TO-SERIAL
INPUT BUFFER
8
OUTPUT BUFFER
AUDIO OUTPUT
FIFO
24 DWORDS
AUDIO INPUT
FIFO
24 DWORDS
32
相關(guān)PDF資料
PDF描述
935269481115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269480115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269479115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269476115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269478115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
935269544557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3
935269987557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557
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935270792557 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
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