參數(shù)資料
型號： 935269343557
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT322-2, MS-022, QFP-160
文件頁數(shù)： 79/143頁
文件大?。?/td> 696K
代理商： 935269343557
2004 Aug 25
40
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
110
RPS_TO0
21
R
RPS time out error in Task 0: this bit is set when the RPS
Task 0 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 0.
UPLD
20
R
RPS in UPLOAD: this bit is active while RPS uploads the
working registers from the shadow RAM. The bit in the ISR is
set on the falling edge of this status bit.
DEBI_S
19
R
DEBI Status: this bit stays set as long as DEBI is processing
or halted by an error. The bit in the ISR is set on the falling
edge of this status bit, which indicates a ‘DEBI Done’.
DEBI_E
18
R
DEBI Event: this bit is set when one of the two DEBI event
ags (DEBI_EF or DEBI_TO) in the SSR is set. This bit is
reset when a new DEBI command starts. The reset value of
DEBI_TO is a logic 1.
IIC_S
17
R
I2C-bus Status: this bit stays set as long as the I2C-bus is
transmitting data or halted by an error. The bit in the ISR is set
on the falling edge of this status bit, which indicates an
‘I2C-bus Done’.
IIC_E
16
R
I2C-bus Error: this bit gets set when one of the I2C-bus status
bits in the SSR is set. This bit is reset when a new I2C-bus
transfer starts.
A2_in
15
R
Audio input DMA2 protection: this bit is set when the audio
input DMA2 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
A2_out
14
R
Audio output DMA2 protection: this bit is set when the audio
output DMA2 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
A1_in
13
R
Audio input DMA1 protection: this bit is set when the audio
input DMA1 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
A1_out
12
R
Audio output DMA1 protection: this bit is set when the audio
output DMA1 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
AFOU
11
R
Audio FIFO Overow/Underow: this bit gets set when one
of the four audio FIFOs has an underow or overow.
V_PE
10
R
Video address Protection Error: this bit is set when one of
the video DMAs 1 to 3 has an address protection error during
an active transmission.
VFOU
9
R
Video FIFO Overow/Underow: this bit is set if any of the
video FIFOs 1, 2 or 3 has an overow or underow.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
RESET
相關PDF資料
PDF描述
935269481115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269480115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269479115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269476115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
935269478115 0.3 A SWITCHING REGULATOR, 57.5 kHz SWITCHING FREQ-MAX, PDSO5
相關代理商/技術參數(shù)
參數(shù)描述
935269544557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3
935269987557 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557
935270713557 制造商:NXP Semiconductors 功能描述:SUB ONLY IC CHP
935270792551 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
935270792557 制造商:NXP Semiconductors 功能描述:IC BUFF DVR TRI-ST 16BIT 56VFBGA
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