參數(shù)資料
型號(hào)： 87LPC769
廠商： NXP Semiconductors N.V.
英文描述： Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and DAC(帶4 kB OTP、8位A/D和D/A轉(zhuǎn)換的低功耗，低價(jià)格，少引腳（20引腳）的微控制器)
中文描述： 低功耗，低價(jià)格，低引腳數(shù)（20針）與4 KB的檢察官辦公室和8位A / D，和DAC（帶4 KB的檢察官辦公室，8位微控制器的A / D和的D / A轉(zhuǎn)換的低功耗，低價(jià)格，少引腳（20引腳）的微控制器）
文件頁(yè)數(shù)： 50/61頁(yè)
文件大?。?/td> 275K
代理商： 87LPC769
Philips Semiconductors
Preliminary specification
87LPC769
Low power, low price, low pin count (20 pin)
microcontroller with 4 kB OTP 8-bit A/D, and DAC
2000 Apr 26
47
SU01182
WATCHDOG
INTERRUPT
S
Q
20-BIT COUNTER
STATE CLOCK
WDTE (UCFG1.7)
BOD (xxx.x)
POR (xxx.x)
WATCHDOG
RESET
CLEAR
8 MSBs
8 TO 1 MUX
WATCHDOG
FEED DETECT
WDOVF
(WDCON.5)
WDS2–0
(WDCON.2–0)
WDTE + WDRUN
WDCLK * WDTE
500 kHz
R/C OSCILLATOR
ENABLE
CLOCK OUT
R
Figure 36. Block Diagram of the Watchdog Timer
BIT
WDCON.7, 6
WDCON.5
SYMBOL
—
WDOVF
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
Watchdog rate select.
Timeout Clocks
Minimum Time
Nominal Time
8,192
10 ms
16,384
20 ms
32,768
41 ms
65,536
82 ms
131,072
165 ms
262,144
330 ms
524,288
660 ms
1,048,576
1.3 sec
WDCON.4
WDRUN
WDCON.3
WDCLK
WDCON.2–0 WDS2–0
WDS2–0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Maximum Time
23 ms
45 ms
90 ms
180 ms
360 ms
719 ms
1.44 sec
2.9 sec
16 ms
32 ms
65 ms
131 ms
262 ms
524 ms
1.05 sec
2.1 sec
WDS0
SU01183
WDS1
WDS2
WDCLK
WDRUN
WDOVF
—
—
0
1
2
3
4
5
6
7
WDCON
Reset Value: 30h for a watchdog reset.
10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
Not Bit Addressable
Address: A7h
Figure 37. Watchdog Timer Control Register (WDCON)
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