參數(shù)資料
型號(hào): 87LPC768
廠商: NXP Semiconductors N.V.
英文描述: Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗,低價(jià)格,少引腳(20引腳)的微控制器)
中文描述: 低功耗,低價(jià)格,低引腳數(shù)(20針)與4 KB的OTP和8位A / D和脈寬調(diào)制器(帶4 KB的檢察官辦公室,8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器,低價(jià)格,少引腳(20引腳)的微控制器)
文件頁(yè)數(shù): 7/66頁(yè)
文件大?。?/td> 314K
代理商: 87LPC768
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
5
PIN DESCRIPTIONS
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
P0.0–P0.7
1, 13, 14,
16–20
I/O
Port 0
: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches are configured in
the quasi-bidirectional mode and have either ones or zeros written to them during reset, as determined
by the PRHI bit in the UCFG1 configuration byte. The operation of port 0 pins as inputs and outputs
depends upon the port configuration selected. Each port pin is configured independently. Refer to the
section on I/O port configuration and the DC Electrical Characteristics for details.
The Keyboard Interrupt feature operates with port 0 pins.
Port 0 also provides various special functions as described below.
1
O
P0.0
CMP2
Comparator 2 output.
PWM3
Pulse Width Modulator 3 output.
20
I
P0.1
CIN2B
Comparator 2 positive input B.
PWM0
Pulse Width Modulator 0 output.
19
I
P0.2
CIN2A
Comparator 2 positive input A.
BRAKE
PWM brake input.
18
I
P0.3
CIN1B
AD0
Comparator 1 positive input B.
A/D channel 0 input.
17
I
P0.4
CIN1A
AD1
Comparator 1 positive input A.
A/D channel 1 input.
16
I
P0.5
CMPREF
AD2
Comparator reference (negative) input.
A/D channel 2 input.
14
O
P0.6
CMP1
AD3
Comparator 1 output.
A/D channel 3 input.
13
I/O
P0.7
T1
Timer/counter 1 external count input or overflow output.
P1.0–P1.7
2–4, 8–12
I/O
Port 1
: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted
below. Port 1 latches are configured in the quasi-bidirectional mode and have either ones or zeros
written to them during reset, as determined by the PRHI bit in the UCFG1 configuration byte. The
operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration
selected. Each of the configurable port pins are programmed independently. Refer to the section on I/O
port configuration and the DC Electrical Characteristics for details.
Port 1 also provides various special functions as described below.
12
O
P1.0
TxD
Transmitter output for the serial port.
11
I
P1.1
RxD
Receiver input for the serial port.
10
I/O
I/O
P1.2
T0
SCL
Timer/counter 0 external count input or overflow output.
I
2
C serial clock input/output. When configured as an output, P1.2 is open
drain, in order to conform to I
2
C specifications.
9
I
I/O
P1.3
INT0
SDA
External interrupt 0 input.
I
2
C serial data input/output. When configured as an output, P1.3 is open
drain, in order to conform to I
2
C specifications.
8
I
P1.4
INT1
External interrupt 1 input.
4
I
P1.5
RST
External Reset input (if selected via EPROM configuration). A low on this pin
resets the microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor begins execution at address 0. When used
as a port pin, P1.5 is a Schmitt trigger input only.
3
O
P1.6
PWM1
Pulse Width Modulator 1 output
2
O
P1.7
PWM2
Pulse Width Modulator 2 output
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