參數(shù)資料
型號： 87LPC768
廠商： NXP Semiconductors N.V.
英文描述： Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗，低價格，少引腳（20引腳）的微控制器)
中文描述： 低功耗，低價格，低引腳數(shù)（20針）與4 KB的OTP和8位A / D和脈寬調(diào)制器（帶4 KB的檢察官辦公室，8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器，低價格，少引腳（20引腳）的微控制器）
文件頁數(shù)： 13/66頁
文件大?。?/td> 314K
代理商： 87LPC768
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
11
Table 2. Example A/D Conversion Times
CPU Clock Rate
RCCLK = 0
RCCLK = 1
nominal
659
μ
s
39.3
μ
s
23.6
μ
s
20.2
μ
s
minimum
563.4
μ
s
32.4
μ
s
18.9
μ
s
16
μ
s
maximum
757
μ
s
48.9
μ
s
30.1
μ
s
27.1
μ
s
32 kHz
1 MHz
4 MHz
11.0592 MHz
12 MHz
16 MHz
20 MHz
NA
186
μ
s
46.5
μ
s
16.8
μ
s
15.5
μ
s
11.6
μ
s
9.3
μ
s
Note: Do not clock ADC from the RC oscillator when MCU clock is greater than 4 MHz.
AD0 (P0.3)
AD1 (P0.4)
V
REF
+ = V
DD
AADR1
AD2 (P0.5)
AD3 (P0.6)
00
01
10
11
V
REF
- = V
SS
ADCON
A/D Converter
AADR0
DAC0
(A/D result)
SU01356
Figure 3. A/D Converter Connections
The A/D in Power Down and Idle Modes
While using the CPU clock as the A/D clock source, the Idle mode
may be used to conserve power and/or to minimize system noise
during the conversion. CPU operation will resume and Idle mode
terminate automatically when a conversion is complete if the A/D
interrupt is active. In Idle mode, noise from the CPU itself is
eliminated, but noise from the oscillator and any other on-chip
peripherals that are running will remain.
The CPU may be put into Power Down mode when the A/D is
clocked by the on-chip RC oscillator (RCCLK=1). This mode gives
the best possible A/D accuracy by eliminating most on-chip noise
sources.
If the Power Down mode is entered while the A/D is running from the
CPU clock (RCCLK=0), the A/D will abort operation and will not
wake up the CPU. The contents of DAC0 will be invalid when
operation does resume.
When an A/D conversion is started, Power Down or Idle mode must
be activated within two machine cycles in order to have the most
accurate A/D result. These two machine cycles are counted at the
CPU clock rate. When using the A/D with either Power Down or Idle
mode, care must be taken to insure that the CPU is not restarted by
another interrupt until the A/D conversion is complete. The possible
causes of wakeup are different in Power Down and Idle modes.
A/D accuracy is also affected by noise generated elsewhere in the
application, power supply noise, and power supply regulation. Since
the 87LPC768 power pins are also used as the A/D reference and
supply, the power supply has a very direct affect on the accuracy of
A/D readings. Using the A/D without Power Down mode while the
clock is divided through the use of CLKR or DIVM has an adverse
effect on A/D accuracy.
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