參數(shù)資料
型號： 87LPC768
廠商： NXP Semiconductors N.V.
英文描述： Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗，低價格，少引腳（20引腳）的微控制器)
中文描述： 低功耗，低價格，低引腳數(shù)（20針）與4 KB的OTP和8位A / D和脈寬調(diào)制器（帶4 KB的檢察官辦公室，8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器，低價格，少引腳（20引腳）的微控制器）
文件頁數(shù)： 37/66頁
文件大小： 314K
代理商： 87LPC768
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
35
Low Voltage EPROM Operation
The EPROM array contains some analog circuits that are not
required when V
DD
is less than 4 V, but are required for a V
DD
greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
power down these analog circuits resulting in a reduced supply
current. LPEP is cleared only by power-on reset, so it may be set
ONLY for applications that always operate with V
DD
less than 4 V.
Reset
The 87LPC768 has an active low reset input when configured for an
external reset. A fully internal reset may also be configured which
provides a reset when power is initially applied to the device. The
watchdog timer can act as an oscillator fail detect because it uses
an independent, fully on-chip oscillator.
The external reset input is disabled, and fully internal reset
generation enabled, by programming the RPD bit in the EPROM
configuration register UCFG1 to 0. EPROM configuration is
described in the section EPROM Characteristics
SU01391
87LPC768
87LPC768
V
DD
8.2 k
10 F
RST
RST
2.2 F
Figure 23. Typical External Reset Circuits
SU01170
CHIP RESET
CPU
CLOCK
Q
RESET
TIMING
RPD (UCFG1.6)
WDT
MODULE
SOFTWARE RESET
SRST (AUXR1.3)
POWER MONITOR
RESET
RST/V
PP
PIN
WDTE (UCFG1.7)
S
R
Figure 24. Block Diagram Showing Reset Sources
相關(guān)PDF資料
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