參數(shù)資料
型號： 87LPC768
廠商： NXP Semiconductors N.V.
英文描述： Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗，低價格，少引腳（20引腳）的微控制器)
中文描述： 低功耗，低價格，低引腳數(shù)（20針）與4 KB的OTP和8位A / D和脈寬調(diào)制器（帶4 KB的檢察官辦公室，8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器，低價格，少引腳（20引腳）的微控制器）
文件頁數(shù)： 23/66頁
文件大小： 314K
代理商： 87LPC768
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
21
BIT
I2CON.7
“
I2CON.6
“
SYMBOL
RDAT
CXA
ATN
IDLE
FUNCTION
Read: the most recently received data bit.
Write: clears the transmit active flag.
Read: ATN = 1 if any of the flags DRDY, ARL, STP, or STP = 1.
Write: in the I
2
C slave mode, writing a 1 to this bit causes the I
2
C hardware to ignore the bus until it
is needed again.
Read: Data Ready flag, set when there is a rising edge on SCL.
Write: writing a 1 to this bit clears the DRDY flag.
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
Write: writing a 1 to this bit clears the CARL flag.
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STR flag.
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
Write: writing a 1 to this bit clears the STP flag.
Read: indicates whether this device is currently as bus master.
Write: writing a 1 to this bit causes a repeated start condition to be generated.
Read: undefined.
Write: writing a 1 to this bit causes a stop condition to be generated.
I2CON.5
“
I2CON.4
“
I2CON.3
“
I2CON.2
“
I2CON.1
“
I2CON.0
“
DRDY
CDR
ARL
CARL
STR
CSTR
STP
CSTP
MASTER
XSTR
—
XSTP
* Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by
use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register
are different. Testing of I2CON bits via the JB and JNB instructions is supported.
—
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable*
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
Figure 9. I
2
C Control Register (I2CON)
BIT
I2DAT.7
SYMBOL
RDAT
FUNCTION
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
Unused.
“
XDAT
I2DAT.6–0
–
—
SU01156
—
—
—
—
—
—
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
—
—
—
—
—
—
—
XDAT
READ
WRITE
Figure 10. I
2
C Data Register (
I
2DAT)
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