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參數(shù)資料
| 型號(hào)： | 87LPC768 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗，低價(jià)格，少引腳（20引腳）的微控制器) |
| 中文描述： | 低功耗，低價(jià)格，低引腳數(shù)（20針）與4 KB的OTP和8位A / D和脈寬調(diào)制器（帶4 KB的檢察官辦公室，8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器，低價(jià)格，少引腳（20引腳）的微控制器） |
| 文件頁(yè)數(shù)： | 19/66頁(yè) |
| 文件大小： | 314K |
| 代理商： | 87LPC768 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
17
The width of each PWM output pulse is determined by the value in
the appropriate compare shadow registers, CPSW0 through
CPSW4, CPSW0–3 for bits 0–7 and CPSW4 for bits 7 and 8. When
the counter described above reaches underflow the PWM output is
forced high. It remains high until the compare value is reached at
which point it goes low until the next underflow. The number of
microcontroller clock pulses that the PWM
n
output is high is given
by:
t
HI
= (CNSW – CPSW
n
+1)
A compare value greater than the counter reload value results in the
PWM output being permanently high. In addition there are two
special cases. A compare value of all zeroes, 000, causes the
output to remain permanently high. A compare value of all ones,
3FF, results in the PWM output remaining permanently low. Again
the compare value is loaded into a shadow register. The transfer
from this holding register to the actual compare register is under
program control.
The register assignments are shown below where the number
immediately following “CPSW” identifies the PWM output. Thus
CPSW0 controls the width of PWM0, CPSW1 the width of PWM1
etc. In the case of two digits following “CPSW,” e.g. CPSW00, the
second digit refers to the bit of the compare value. Thus CPSW00
represents the value loaded into bit 0 of the PWM0 compare register
CPSW0: Compare Shadow register 0
Addr:
Reset Value:
0D3H
00H
7
6
5
4
3
2
1
0
CPSW07
CPSW06
CPSW05
CPSW04
CPSW03
CPSW02
CPSW01
CPSW00
CPSW1: Compare Shadow register 1
Addr:
Reset Value:
0D4H
00H
7
6
5
4
3
2
1
0
CPSW17
CPSW16
CPSW15
CPSW14
CPSW13
CPSW12
CPSW11
CPSW10
CPSW2: Compare Shadow register 2
Addr:
Reset Value:
0D5H
00H
7
6
5
4
3
2
1
0
CPSW27
CPSW26
CPSW25
CPSW24
CPSW23
CPSW22
CPSW21
CPSW20
CPSW3: Compare Shadow register 3
Addr:
Reset Value:
0D6H
00H
7
6
5
4
3
2
1
0
CPSW37
CPSW36
CPSW35
CPSW34
CPSW33
CPSW32
CPSW31
CPSW30
CPSW4: Compare Shadow register 4
Addr:
Reset Value:
0D7H
00H
7
6
5
4
3
2
1
0
CPSW39
CPSW38
CPSW29
CPSW28
CPSW19
CPSW18
CPSW09
CPSW08
The overall functioning of the PWM module is controlled by the
contents of the PWMCON0 register. The operation of most of the
control bits is straightforward. For example there is an invert bit for
each output which causes results in the output to have the opposite
value compared to its non-inverted output. The transfer of the data
from the shadow registers to the control registers is controlled by the
PWMCON0.6 while PWMCON0.7 allows the PWM to be either in
the run or idle state. The user can monitor when underflow causes
the transfer to occur by monitoring the Transfer bit, PWCON0.6.
When the transfer takes place the PWM logic automatically resets
this bit.
The fact that the transfer from the shadow to the working registers
only occurs when there is an underflow in the counter results in the
need for the user’s program to observe the following precautions. If
PWMCON1 is written with Transfer set without Run being enabled
the transfer will never take place. Thus if a subsequent write sets
Run without Transfer the compare and counter values will not be
those expected. If Transfer and Run are set, and prior to underflow
there is a subsequent load of PWMCON0 which sets Run but not
Transfer, the transfer will never take place. Again the compare and
counter values that existed prior to the update attempt will be used.
As outlined above the Transfer bit can be polled to determine when
the transfer occurs. Unless there is a compelling reason to do
otherwise, it is recommended that both Run, PWMCON0.7, and
Transfer, PWMCON0.7, be set when PWMCON0 is written.
When the Run bit, PWMCON0.7, is cleared the PWM outputs take
on the state they had just prior to the bit being cleared. In general
this state is not known. In order to place the outputs in a known
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