
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
8
Name
Reset
Value
Bit Functions and Addresses
MSB
LSB
SFR
Address
Description
KBI#
Keyboard Interrupt
86h
00h
87
T1
97
86
85
84
83
82
81
80
P0*
Port 0
80h
CMP1
96
(P1.6)
A6
–
CMPREF
95
RST
A5
–
CIN1A
94
INT1
A4
–
CIN1B
93
INT0
A3
–
CIN2A
92
T0
A2
–
CIN2B
91
RxD
A1
X1
CMP2
90
TxD
A0
X2
Note 2
P1*
Port 1
90h
(P1.7)
A7
–
Note 2
P2*
P0M1#
P0M2#
P1M1#
P1M2#
P2M1#
P2M2#
PCON
Port 2
Port 0 output mode 1
Port 0 output mode 2
Port 1 output mode 1
Port 1 output mode 2
Port 2 output mode 1
Port 2 output mode 2
Power control register
A0h
84h
85h
91h
92h
A4h
A5h
87h
Note 2
00h
00H
00h
1
00h
1
00h
00h
1
Note 3
(P0M1.7)
(P0M1.6)
(P0M1.5)
(P0M1.4)
(P0M1.3)
(P0M1.2)
(P0M1.1)
(P0M1.0)
(P0M2.7)
(P0M2.6)
(P0M2.5)
–
–
P0S
–
BOF
D5
F0
(P0M2.4)
(P0M2.3)
–
–
T1OE
–
GF1
D3
RS0
(P0M2.2)
–
–
T0OE
–
GF0
D2
OV
(P0M2.1)
(P0M2.0)
(P1M1.7)
(P1M1.6)
(P1M1.4)
(P1M1.1)
(P1M1.0)
(P1M2.7)
P2S
–
SMOD1
D7
CY
(P1M2.6)
P1S
–
SMOD0
D6
AC
(P1M2.4)
ENCLK
–
POF
D4
RS1
(P1M2.1)
(P1M2.0)
(P2M1.1)
(P2M1.0)
(P2M2.1)
PD
D1
F1
(P2M2.0)
IDL
D0
P
PSW*
PT0AD#
Program status word
Port 0 digital input disable
D0h
F6h
00h
00h
9F
9E
9D
9C
9B
9A
99
98
PWMCON0
PWMCON1
SCON*
PWM Control Register 0
PWMControl Register 1
Serial port control
Serial port data buffer
register
Serial port address register
Serial port address enable
Stack pointer
DAh
DBh
98h
RUN
BKCH
SM0
XFER
BKPS
SM1
PWM3I
BPEN
SM2
PWM2I
BKEN
REN
–
PWM3B
TB8
PWM1I
PWM2B
RB8
PWM0I
PWM1B
TI
–
PWM0B
RI
00h
00h
00h
SBUF
99h
xxh
SADDR#
SADEN#
SP
A9h
B9h
81h
00h
00h
07h
8F
TF1
8E
TR1
8D
TF0
8C
TR0
8B
IE1
8A
IT1
89
IE0
88
IT0
TCON*
TH0
TH1
TL0
TL1
TMOD
Timer 0 and 1 control
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
Timer 0 and 1 mode
88h
8Ch
8Dh
8Ah
8Bh
89h
00h
00h
00h
00h
00h
00h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
WDCON#
WDRST#
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0.
2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte.
3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up.
4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
Watchdog control register
Watchdog reset register
A7h
A6h
–
–
WDOVF
WDRUN
WDCLK
WDS2
WDS1
WDS0
Note 4
xxh