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參數(shù)資料
| 型號： | 87LPC768 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low power, low price, low pin count(20 pin) microcontroller with 4 kB OTP and 8-bit A/D,and Pulse Width Modulator(帶4 kB OTP、8位A/D和脈寬調(diào)節(jié)的低功耗，低價格，少引腳（20引腳）的微控制器) |
| 中文描述： | 低功耗，低價格，低引腳數(shù)（20針）與4 KB的OTP和8位A / D和脈寬調(diào)制器（帶4 KB的檢察官辦公室，8位A / D轉(zhuǎn)換和脈寬調(diào)節(jié)的低功耗微控制器，低價格，少引腳（20引腳）的微控制器） |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 314K |
| 代理商： | 87LPC768 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
23
BIT
I2CFG.7
SYMBOL
SLAVEN
FUNCTION
Slave Enable. Writing a 1 this bit enables the slave functions of the I
2
C subsystem. If SLAVEN and
MASTRQ are 0, the I
2
C hardware is disabled. This bit is cleared to 0 by reset and by an I
2
C
time-out.
Master Request. Writing a 1 to this bit requests mastership of the I
2
C bus. If a transmission is in
progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. A
start condition is sent and DRDY is set (thus making ATN = 1 and generating an I
2
C interrupt).
When a master wishes to release mastership status of the I
2
C, it writes a 1 to XSTP in I2CON.
MASTRQ is cleared by an I
2
C time-out.
Writing a 1 to this bit clears the Timer I overflow flag. This bit position always reads as a 0.
Writing a 1 to this bit lets Timer I run; a zero stops and clears it. Together with SLAVEN, MASTRQ,
and MASTER, this bit determines operational modes as shown in Table 1.
Reserved for future use. Should not be set to 1 by user programs.
These two bits are programmed as a function of the CPU clock rate, to optimize the MIN HI and LO
time of SCL when this device is a master on the I
2
C. The time value determined by these bits
controls both of these parameters, and also the timing for stop and start conditions.
I2CFG.6
MASTRQ
I2CFG.5
I2CFG.4
CLRTI
TIRUN
I2CFG.2, 3
I2CFG.1, 0 CT1, CT0
—
CT0
SU01157
CT1
—
—
TIRUN
CLRTI
MASTRQ
SLAVEN
0
1
2
3
4
5
6
7
I2CFG
Reset Value: 00h
Not Bit Addressable
Address: C8h
Figure 11. I
2
C Configuration Register (I2CFG)
Regarding Software Response Time
Because the 87LPC768 can run at 20 MHz, and because the I
2
C
interface is optimized for high-speed operation, it is quite likely that
an I
2
C service routine will sometimes respond to DRDY (which is set
at a rising edge of SCL) and write I2DAT before SCL has gone low
again. If XDAT were applied directly to SDA, this situation would
produce an I
2
C protocol violation. The programmer need not worry
about this possibility because XDAT is applied to SDA only when
SCL is low.
Conversely, a program that includes an I
2
C service routine may take
a long time to respond to DRDY. Typically, an I
2
C routine operates
on a flag-polling basis during a message, with interrupts from other
peripheral functions enabled. If an interrupt occurs, it will delay the
response of the I
2
C service routine. The programmer need not worry
about this very much either, because the I
2
C hardware stretches the
SCL low time until the service routine responds. The only constraint
on the response is that it must not exceed the Timer I time-out.
Values to be used in the CT1 and CT0 bits are shown in Table 2. To
allow the I
2
C bus to run at the maximum rate for a particular
oscillator frequency, compare the actual oscillator rate to the f OSC
max column in the table. The value for CT1 and CT0 is found in the
first line of the table where CPU clock max is greater than or equal
to the actual frequency.
Table 2 also shows the machine cycle count for various settings of
CT1/CT0. This allows calculation of the actual minimum high and
low times for SCL as follows:
SCL min high low time (in microseconds)
6 * Min Time Count
CPU clock (in MHz)
For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the
minimum SCL high and low times will be 5.25
μ
s.
Table 2 also shows the Timer I timeout period (given in machine
cycles) for each CT1/CT0 combination. The timeout period varies
because of the way in which minimum SCL high and low times are
measured. When the I
2
C interface is operating, Timer I is pre-loaded
at every SCL transition with a value dependent upon CT1/CT0. The
pre-load value is chosen such that a minimum SCL high or low time
has elapsed when Timer I reaches a count of 008 (the actual value
pre-loaded into Timer I is 8 minus the machine cycle count).
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