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參數(shù)資料
| 型號(hào)： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁數(shù)： | 43/51頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision 1.0
Page 39
5.2.2 Legacy Support Registers
Four registers are provided for legacy support:
1. HceControl
-
Used to enable and control the emulation hardware and report various status information.
2. HceInput
-
Emulation side of the legacy Input Buffer register.
3. HceOutput
-
Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software.
4. HceStatus
-
Emulation side of the legacy Status register.
These registers are located in the Host Controller Register Space; from MEMOFST 100h through 10Fh. The bit formats for
these registers are described in Table 5-3.
Refer to "Legacy Support" section for information when accessing these registers when emulation is enabled.
5.2.3 MEMOFST 100h-1Fh (Legacy Support Registers)
7
6
5
4
3
2
1
0
MEMOFST 100h
HceControl Register - Byte 0
Default = 00h
IRQ12 Active
Indicates that a
positive
transition of
IRQ12 from
kybrd controller
has occurred.
Writing a 1
clears this bit,
while writing a 0
leaves it
unchanged.
IRQ1 Active
Indicates that a
positive
transition of
IRQ1 from
kybrd controller
has occurred.
Writing a 1
clears this bit,
while writing a 0
leaves it
unchanged.
GateA20
Sequence
Set by HC
when a data
value of D1h is
written to Port
64h.
Cleared by HC
on write to Port
64h of any
value other than
D1h.
External
IRQEn
IRQ1 and
IRQ12 from
kybrd controller
causes
emulation
interrupt:
0 = Disable
1 = Enable
This bit is
independent of
the Emulation
Enable bit (bit
0) setting.
IRQEn
If the Output
Full bit
(MEMOFST
10Ch[0]) = 1,
HC generates
IRQ1 or IRQ12.
If the Aux
Output Full bit
(MEMOFST
10Ch[5]) = 0,
HC generates
IRQ1; if = 1, HC
generates
IRQ12.
0 = Disable
1 = Enable
Character
Pending
HC generates
emulation
interrupt when
the Output Full
bit (MEMOFST
10Ch[0]) = 0.
0 = Disable
1 = Enable
Emulation
Interrupt (RO)
A static decode
of the emulation
interrupt
condition.
Emulation
Enable
HC is enabled
for legacy
emulation
0 = No
1 = Yes(1)
(1) The HC decodes accesses to Ports 60h/64h and generates IRQ1 and/or IRQ12 when appropriate. Additionally, the HC generates an
emulation interrupt at appropriate times to invoke the emulation software.
MEMOFST 101h
HceControl Register - Byte 1
Default = 00h
Reserved
A20 State:
Indicates
current state of
Gate A20 on
kybrd controller.
Used to
compare
against value
written to Port
60h when
GateA20
Sequence is
active.
MEMOFST 102h-103h
HceControl Register - Bytes 2 & 3
Default = 00h
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