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參數(shù)資料
| 型號： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁數(shù)： | 35/51頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision 1.0
Page 31
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0
MEMOFST 10h
HcInterruptEnable Register - Byte 0*
Default = 00h
Reserved
Allow interrupt
generation due
to Root Hub
Status
Change:
0 = Ignore
1 = Enable
Allow interrupt
generation due
to Frame
Number
Overflow:
0 = Ignore
1 = Enable
Reserved
All writes to this
bit are ignored.
Allow interrupt
generation due
to Resume
Detected:
0 = Ignore
1 = Enable
Allow interrupt
generation due
to Start of
Frame:
0 = Ignore
1 = Enable
Allow interrupt
generation due
to Writeback
Done Head:
0 = Ignore
1 = Enable
Allow interrupt
generation due
to Scheduling
Overrun:
0 = Ignore
1 = Enable
MEMOFST 11h-12h
HcInterruptEnable Register - Bytes 1 & 2
Default = 00h
Reserved
MEMOFST 13h
HcInterruptEnable Register - Byte 3*
Default = 00h
Master
interrupt
generation:
0 = Ignore
1 = Allows all
interrupts to
be enabled
in 10h-13h.
* Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Allow interrupt
generation due
to Ownership
Change:
0 = Ignore
1 = Enable
Reserved
MEMOFST 14h
HcInterruptDisable Register - Byte 0*
Default = 00h
Reserved
Allow interrupt
generation due
to Root Hub
Status
Change:
0 = Ignore
1 = Disable
Allow interrupt
generation due
to Frame
Number
Overflow:
0 = Ignore
1 = Disable
Reserved
All writes to this
bit are ignored.
Allow interrupt
generation due
to Resume
Detected:
0 = Ignore
1 = Disable
Allow interrupt
generation due
to Start of
Frame:
0 = Ignore
1 = Disable
Allow interrupt
generation due
to Writeback
Done Head:
0 = Ignore
1 = Disable
Allow interrupt
generation due
to Scheduling
Overrun:
0 = Ignore
1 = Disable
MEMOFST 15h-16h
HcInterruptDisable Register - Bytes 1 & 2
Default = 00h
Reserved
MEMOFST 17h
HcInterruptDisable Register - Byte 3*
Default = 00h
Master
interrupt
generation:
0 = Ignore
1 = Allows all
interrupts to
be disabled
in 10h-13h.
* Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged.
Allow interrupt
generation due
to Ownership
Change:
0 = Ignore
1 = Disable
Reserved
MEMOFST 18h-1Bh
HcHCCA Register
Default = 00h
Bits [31:0] correspond to: 18h = [7:0], 19h = [15:8], 1Ah = [23:16], 1Bh = [31:24].
- Bits [7:0]
Reserved
- Bits [31:8]
Pointer to HCCA base address
MEMOFST 1Ch-1Fh
HcPeriodCurrentED Register
Default = 00h
Bits [31:0] correspond to: 1Ch = [7:0], 1Dh = [15:8], 1Eh = [23:16], 1Fh = [31:24].
- Bits [3:0]
Reserved
- Bits [31:4]
Pointer to current Periodic List End Descriptor
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PDF描述 |
|---|---|
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| 82C871(100QFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BUS CONTROLLER |
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