參數(shù)資料
型號(hào)： 82C862
廠商： Electronic Theatre Controls, Inc.
英文描述： FireLink USB Dual Controller Quad Port USB
中文描述： FireLink雙控制器的USB四口USB
文件頁數(shù)： 33/51頁
文件大?。?/td> 321K
代理商： 82C862
FireLink USB
82C862
912-2000-030
Revision 1.0
Page 29
5.2
Host Controller Register Space
This register space is the operational control block in the USB core. It is responsible for the host controller operational states
(Suspend, Disabled, Enabled), special USB signaling (Reset, Resume), status, interrupt control, and host controller
configuration information.
The host controller (HC) interface registers are PCI memory mapped I/O, hereafter referred to as MEMOFST. The bit formats
for these registers are described in Table 5-2.
5.2.1 MEMOFST 00h-5Ch
7
6
5
4
3
2
1
0
MEMOFST 00h
MEMOFST 01h-03h
HcRevision Register (RO)
Default = 10h
Default = 000001h
Bits [31:0] correspond to: 00h = [7:0], 01h = [15:8], 02h = [23:16], 03h = [31:24]
- Bits [7:0]
Revision - Indicates the Open HCI Specification revision number implemented by hardware (X.Y = XYh).
FireLink support Specification 1.0.
- Bits [31:8]
Reserved
MEMOFST 04h
HcControl Register - Byte 0
Default = 00h
HC Functional State:
00 = USB Reset
01 = USB Resume
10 = USB Operational
11 = USB Suspend
The HC may force a state change
from USB Suspend to USB
Resume after detecting resume
signaling from a downstream port.
Processing of
Bulk List:
0 = Disable
1 = Enable
Processing of
Control List:
0 = Disable
1 = Enable
Disable
Isochronous
List when
Periodic List is
enabled:(1)
0 = Yes
1 = No
Processing of
Periodic
(interrupt and
isochronous)
List:
0 = Disable
1 = Enable
The HC checks
this bit prior to
attempting any
periodic
transfers in a
frame.
Control Bulk Service Ratio:
Specifies the number of control
endpoints serviced for every bulk
endpoint. Encoding is ND1 where
N is the number of control
endpoints (i.e., 00 = 1 control
endpoint; 11 = 4 control
endpoints).
(1) Disabling the Isochronous List when the Periodic List is enabled allows interrupt endpoint descriptors to be serviced. While processing
the Period List, the HC will check bit 3 when it finds an isochronous endpoint descriptor.
MEMOFST 05h
HcControl Register - Byte 1
Default = 00h
Reserved
Remote
Wakeup
Connected
Enable:
If a remote
wakeup signal
is supported,
this bit is used
to enable that
operation.
Since there is
no remote
wakeup signal
supported, this
bit is ignored.
Remote
Wakeup
Connected
(RO):
Indicates
whether the HC
supports a
remote wakeup
signal. This
implementation
does not
support any
such signal.
The bit is
hardcoded to 0.
Interrupt
Routing:
0 = Interrupts
routed to
normal
interrupt
mechanism
(INTA#)
1 = Interrupts
routed to
SMI
MEMOFST 06h-07h
HcControl Register - Bytes 2 & 3
Default = 00h
Reserved
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