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參數(shù)資料
| 型號： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁數(shù)： | 18/51頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision: 1.0
Page 14
4.2
PCI Controller
The PCI controller interfaces the host controller to the PCI bus. As a master, the PCI controller is responsible for running
cycles on the PCI bus on behalf of the host controller. As a target, the PCI controller monitors the cycles on the PCI bus and
determines when to respond to these cycles. A USB host controller module is a PCI target when it decodes cycles to its
internal PCI configuration registers or to its internal PCI memory mapped I/O registers. The PCI controller asserts DEVSEL# in
medium decode timing to claim a PCI transaction.
Since two PCI-interfaced USB controller modules reside on-chip, the logic includes an internal arbiter to select between the
two modules when one or both make a bus mastering request.
The PCI configuration space of the primary USB host controller module is accessed as Device #X, Function #0, where Device
#X depends on which AD line is connected to the IDSEL input. For the secondary USB host controller module, PCI
configuration register space is accessed as Function #1 instead. PCI configuration space is hereafter referred to as PCICFG.
Table 3 gives a register map of the PCICFG register space (duplicated for each of the two functions). Refer to Section 5.1,
"PCICFG Register Space" for detailed bit information.
Table 3.
PCI Controller Register Map
PCICFG
R/W
Register Name
00h-01h
RO
Vendor ID
02h-03h
RO
Device ID
04h-05h
R/W
Command
06h-07h
R/W
Status
08h
RO
Revision ID
09h-0Bh
RO
Class Code
0Ch
R/W
Cache Line Size
0Dh
R/W
Master Latency Timer
0Eh
RO
Header Type
0Fh
--
Reserved
10h-13h
R/W
Base Address Register 0
14h-2Bh
--
Reserved
2Ch-2Dh
RO
Subsystem Vendor
2Eh-2Fh
RO
Subsystem ID
30h-3Bh
--
Reserved
3Ch
R/W
Interrupt Line
3Dh
R/W
Interrupt Pin
3Eh
R/W
Minimum Grant
PCICFG
R/W
Register Name
3Fh
R/W
Maximum Latency
40h-45h
--
Reserved for factory test
46h-4Bh
--
Reserved
4Ch
R/W
Interrupt Pin Selection
4Dh
R/W
Miscellaneous Control
4Eh-4Fh
--
Reserved
50h
R/W
PCI Host Feature Control
51h
--
Reserved
52h
R/W
Strap Option Override
53h
R/W
GPIO Select
54h
R/W
GPIO Output Enable
55h
R/W
GPIO Data
56h-7Bh
--
Reserved
7Ch-7Fh
R/W
Subsystem ID Restore
80h-EFh
--
Reserved
F0h-F5h
R/W
PCI Power Management
F6h-FFh
--
Reserved
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