B4-B7
F<0:3>
These four bits determine the command to be performed as shown
below.
F3
0
0
0
0
0
0
0
0
1
1
1
1
1
F2
0
0
0
0
1
1
1
1
0
0
0
0
1
F1
0
0
1
1
0
0
1
1
0
0
1
1
X
F0
0
1
0
1
0
1
0
1
0
1
0
1
X
Command
Latch Counter 0 (See Counter Latch Command)
Read/Write counter 0 LSB only
Read/Write counter 0 MSB only
Read/Write counter 0 LSB then MSB
Latch Counter 2 (See Counter Latch Command)
Read/Write counter 1 LSB only
Read/Write counter 1 MSB only
Read/Write counter 1 LSB then MSB
Latch Counter 2 (See Counter Latch Command)
Read/Write Counter 2 LSB only
Read/Write Counter 2 MSB only
Read/Write Counter 2 LSB then MSB
Read-Back command (see Counter Read-Back
Command)
MSB = Most Significant Byte
LSB = Least Significant Byte
X = Don’t care
Read/Write Counter Command
When writing to a counter, two convensions must be observed:
Each counter’s Control Word must be written before the initial count is written.
Writing the initial count must follow the format specified in the Control Word (least
significant byte only, most significant byte only; or least significant byte, then most
significant byte).
A new initial count can be written into the counter any time after programming without
rewriting the Control Word, as long as the programmed format is observed.
During Read/Write Counter Commands M<2:0> are defined as follows:
Select Mode 0
when M2 = 0 and M1 = 0 and M0 = 0
Select Mode 1
when M2 = 0 and M1 = 0 and M0 = 1
Select Mode 2
when M1 = 1 and M0 = 0 (M2 is ‘‘don’t care’’)
Select Mode 3
when M1 = 1 and M0 = 1 (M2 is ‘‘don’t care’’)
Select Mode 4
when M2 = 1 and M1 = 0 and M0 = 0
Select Mode 5
when M2 = 1 and M1 = 0 and M0 = 1
I
Programming the Counter Timer Controller
Real Time Clock and Internal Timer Registers
6-12
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.