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參數(shù)資料
| 型號(hào)： | 82C836A-16 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 123/205頁(yè) |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A-16 |
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The purpose of Index 60H is to allow DRAM refresh to continue during power-down.
Consequently, bits 7-3 are preserved during power-down instead of cleared by
PWRGOOD. To initialize this ICR to its default value, a logic low level on the Power
Sense (MFP5) input is used while PWRGOOD is low.
Table 10-15.
Index 60H----Laptop Features
Bit
Name
Description
7
CAS-Before-RAS
Refresh Enable
0 = RAS only refresh (default)
1 = CAS before RAS refresh
6
Stand-by Refresh
Enable (also known
as Stand-by mode)
This mode allows local DRAM refreshing to continue during power-down.
No refresh address is generated during power-down, so CAS-before-RAS
refresh should be enabled and DRAMs that support CAS-before-RAS
refresh should be used. Stand-by refresh relies on the 32KHz input clock
(MFP4 pin), which isn’t available with external RTC (MFP4 becomes
IRQ8). Consequently, stand-by refresh cannot be used with external RTC.
0 = No refresh during power-down (default)
1 = Refresh continues during power-down
This bit, when set to one, has the following additional effects: ICR 4DH bits
4-0 (memory configuration) are preserved during power-down. ICR 4EH bit
6 (MRA enable) is preserved during power-down. DACK signals are no
longer sampled following PWRGOOD rise. PWRGOOD fall (powering
down) takes effect only after stand-by refresh is operational to maintain
refresh continuity. For assured recovery from potential lockup conditions
following initial power turn-on or software malfunction, the 82C836B
contains a built-in 32KHz based timeout and external RTC interlock to clear
this bit automatically under abnormal conditions. PWRGOOD can then take
effect in the normal manner without standby mode
5-4
Stand-by
Refresh Interval
Allows reduced power consumption for stand-by refresh during power-
down via reduced DRAM refresh rate if compatible DRAMs are used.
The reduced refresh rate takes effect only during power-down and only
if stand-by refresh is enabled.
00 = 15
μ
s (default; half cycle of 32.768KHz input clock)
01 = 61
μ
s (2 cycles of 32.768KHz input clock)
10 = 122
μ
s (4 cycles of 32.768KHz input clock)
11 = 244
μ
s (8 cycles of 32.768KHz input clock)
3
Refresh Time Base
(Read Only)
Indicates whether or not the system has switched from stand-by refresh to
normal. If stand-by mode is enabled, the system switches from 14.3MHz
refresh timing to 32KHz timing during power-down. When power comes
back up, the BIOS must reprogram Timer Channel 1 (see
Section 6,
Programmable Interval Timer
) to get refresh request running again. The
82C836 then switches back to 14.3MHz based refresh. BIOS should not
try to access DRAM until the switch back to 14.3MHz timing has occurred.
The switching of the refresh time base is done in a double-synchronized
manner to prevent any lost or aborted refresh cycles.
0 = 14.3MHz based refresh
1 = 32KHz based refresh
2-0
----
Reserved. Write as 0.
82C386 CHIPSet Data Sheet
Configuration Registers
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
10-11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836A-20 | Single-Chip 386sx AT |
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836A-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
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