Signal Description
2-4
Intel
82801BA ICH2 Datasheet
2.6
IDE Interface
GNT[0:4]#
GNT[5]# /
GNT[B]# /
GPIO[17]#
O
PCI Grants:
Supports up to 6 masters on the PCI bus. GNT[5]# is muxed with
PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI
or PC/PCI, GNT[5]# can instead be used as a GPIO.
Pull-up resistors are not required on these signals. If pullups are used, they should
be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-
up.
PCICLK
I
PCI Clock:
33 MHz clock. PCICLK provides timing for all transactions on the PCI
Bus.
PCIRST#
O
PCI Reset:
ICH2 asserts PCIRST# to reset devices that reside on the PCI bus. The
ICH2 asserts PCIRST# during power-up and when S/W initiates a hard reset
sequence through the RC (CF9h) register. The ICH2 drives PCIRST# inactive a
minimum of 1 ms after PWROK is driven active. The ICH2 drives PCIRST# active a
minimum of 1 ms when initiated through the RC register.
PLOCK#
I/O
PCI Lock:
PLOCK# indicates an exclusive bus operation and may require multiple
transactions to complete. ICH2 asserts PLOCK# when it performs non-exclusive
transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the
bus.
SERR#
I
System Error:
SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the ICH2 has the ability to
generate an NMI, SMI#, or interrupt.
PME#
I
PCI Power Management Event:
PCI peripherals drive PME# to wake the system
from low-power states S1-S5. PME# assertion can also be enabled to generate an
SCI from the S0 state. In some cases the ICH2 may drive PME# active due to an
internal wake event. The ICH2 will not drive PME# high, but it will be pulled up to
VccSus3_3 by an internal pull-up resistor.
REQ[A]# /
GPIO[0]
REQ[B]# /
REQ[5]# /
GPIO[1]
I
PC/PCI DMA Request [A:B]:
This request serializes ISA-like DMA Requests for the
purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by
devices such as PCI-based Super I/O or audio codecs that need to perform legacy
8237 DMA but have no ISA bus.
When not used for PC/PCI requests, these signals can be used as General Purpose
Inputs. Instead, REQ[B]# can be used as the 6th PCI bus request.
GNT[A]# /
GPIO[16]
GNT[B]#
/
GNT[5]# /
GPIO[17]
O
PC/PCI DMA Acknowledges [A:B]:
This grant serializes an ISA-like DACK# for the
purpose of running DMA/ISA master cycles over the PCI bus. This is used by
devices such as PCI-based Super/IO or audio codecs which need to perform legacy
8237 DMA but have no ISA bus.
When not used for PC/PCI, these signals can be used as General Purpose Outputs.
GNTB# can also be used as the 6th PCI bus master grant output. These signal have
internal pull-up resistors.
Table 2-6. IDE Interface Signals
Name
Type
Description
PDCS1#,
SDCS1#
O
Primary and Secondary IDE Device Chip Selects for 100 Range:
These
signals are for the ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE connector.
PDCS3#,
SDCS3#
O
Primary and Secondary IDE Device Chip Select for 300 Range:
These signals
are for the ATA control register block. This output signal is connected to the
corresponding signal on the primary or secondary IDE connector.
Table 2-5. PCI Interface Signals (Continued)
Name
Type
Description
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