Intel
82801BA ICH2 Datasheet
7-5
LAN Controller Registers (B1:D8:F0)
7.1.10
HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
0Eh
00h
Attribute:
Size:
RO
8 bits
7.1.11
CSR_MEM_BASE CSR—Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
10–13h
0000 0008h
Attribute:
Size:
R/W, RO
32 bits
Note:
The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
7.1.12
CSR_IO_BASE—CSR I/O-Mapped Base Address Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
14–17h
0000 0001h
Attribute:
Size:
R/W
32 bits
Note:
The ICH2’s integrated LAN Controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the Lan Controller’s CSR registers.
Bit
Description
7
Multi-function Device
—RO. Hardwired to 0 to indicate a single function device.
6:0
Header Type
—RO.
7-bit field identifies the header layout of the configuration space as an Ethernet
controller.
Bit
Description
31:12
Base Address
—R/W.
Upper 20 bits of the base address provides 4 KB of memory-mapped space for
the LAN Controller’s Control/Status Registers.
11:4
Reserved.
3
Pre-fetchable—RO.
Hardwired to 0 to indicate that this is not a pre-fetchable memory-mapped
address range.
2:1
Type—RO.
Hardwired to 00b to indicate the memory-mapped address range may be located
anywhere in 32-bit address space.
0
Memory-Space Indicator—RO. Hardwired to 0 to indicate that this base address maps to memory
space.
Bit
Description
31:16
Reserved.
15:6
Base Address
—R/W.
Provides 64 bytes of I/O-mapped address space for the LAN Controller’s
Control/Status Registers.
5:1
Reserved.
0
I/O Space Indicator—RO. Hardwired to 1 to indicate that this base address maps to I/O space.
Powered by ICminer.com Electronic-Library Service CopyRight 2003