
SMBus Controller Registers (D31:F3)
12-2
Intel
82801BA ICH2 Datasheet
12.1.3
CMD—Command Register (SMBUS—D31:F3)
Address:
Default Value:
04–05h
0000h
Attributes:
Size:
RO, R/W
16 bits
12.1.4
STA—Device Status Register (SMBUS—D31:F3)
Address:
Default Value:
06–07h
0280h
Attributes:
Size:
RO, R/WC
16 bits
Bit
Description
15:10
Reserved.
9
Fast Back to Back Enable (FBE)—RO. Reserved as 0.
8
SERR# Enable (SERREN)—RO. Reserved as 0.
7
Wait Cycle Control (WCC)—RO. Reserved as 0.
6
Parity Error Response (PER)—RO. Reserved as 0.
5
VGA Palette Snoop (VPS)—RO. Reserved as 0.
4
Postable Memory Write Enable (PMWE)—RO. Reserved as 0.
3
Special Cycle Enable (SCE)—RO. Reserved as 0.
2
Bus Master Enable (BME)—RO. Reserved as 0.
1
Memory Space Enable (MSE)—RO. Reserved as 0.
0
I/O Space Enable (IOSE)—
R/W.
0 = Disable.
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address Register.
Bit
Description
15
Detected Parity Error (DPE)—RO. Reserved as 0.
14
Signaled System Error (SSE)—RO. Reserved as 0.
13
Received Master Abort (RMA)—RO. Reserved as 0.
12
Received Target Abort (RTA)—RO. Reserved as 0.
11
Signaled Target-Abort Status (STA)
—R/WC.
1 = Function is targeted with a transaction that the ICH2 terminates with a target abort.
0 = Software resets STA to 0 by writing a 1 to this bit location.
10:9
DEVSEL# Timing Status (DEVT)
—RO.
This 2-bit field defines the timing for DEVSEL# assertion
for positive decode.
01 = Medium timing.
8
Data Parity Error Detected—RO. Reserved as 0.
7
Fast Back-to-Back Capable—RO. Reserved as 1.
6
User Definable Features (UDF)—RO. Reserved as 0.
5
66 MHz Capable—RO. Reserved as 0.
4:0
Reserved.
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