xvi
82801BA ICH2
Datasheet
9.9
System Management TCO Registers (D31:F0)..........................................9-75
9.9.1
TCO Register I/O Map...................................................................9-75
9.9.2
TCO1_RLD—TCO Timer Reload and Current Value Register......9-75
9.9.3
TCO1_TMR—TCO Timer Initial Value Register............................9-76
9.9.4
TCO1_DAT_IN—TCO Data In Register ........................................9-76
9.9.5
TCO1_DAT_OUT—TCO Data Out Register..................................9-76
9.9.6
TCO1_STS—TCO1 Status Register..............................................9-76
9.9.7
TCO2_STS—TCO2 Status Register..............................................9-78
9.9.8
TCO1_CNT—TCO1 Control Register............................................9-79
9.9.9
TCO2_CNT—TCO2 Control Register............................................9-80
9.9.10 TCO_MESSAGE1 and TCO_MESSAGE2 Registers....................9-80
9.9.11 TCO_WDSTATUS—TCO2 Control Register.................................9-80
9.9.12 SW_IRQ_GEN—Software IRQ Generation Register.....................9-81
General Purpose I/O Registers (D31:F0) ...................................................9-81
9.10.1 GPIO Register I/O Address Map....................................................9-83
9.10.2 GPIO_USE_SEL—GPIO Use Select Register ..............................9-83
9.10.3 GP_IO_SEL—GPIO Input/Output Select Register ........................9-84
9.10.4 GP_LVL—GPIO Level for Input or Output Register.......................9-84
9.10.5 GPO_BLINK—GPO Blink Enable Register....................................9-85
9.10.6 GPI_INV—GPIO Signal Invert Register.........................................9-86
9.10
10
IDE Controller Registers (D31:F1)...........................................................................10-1
10.1
PCI Configuration Registers (IDE—D31:F1) ..............................................10-1
10.1.1 CMD—Command Register (IDE—D31:F1) ...................................10-2
10.1.2 STS—Device Status Register (IDE—D31:F1)...............................10-3
10.1.3 PI—Programming Interface (IDE—D31:F1)...................................10-3
10.1.4 SCC—Sub Class Code (IDE—D31:F1).........................................10-3
10.1.5 BCC—Base Class Code (IDE—D31:F1).......................................10-4
10.1.6 MLT—Master Latency Timer (IDE—D31:F1).................................10-4
10.1.7 BM_BASE—Bus Master Base Address Register
(IDE—D31:F1)...............................................................................10-4
10.1.8 IDE_SVID—Subsystem Vendor ID (IDE—D31:F1).......................10-5
10.1.9 IDE_SID—Subsystem ID (IDE—D31:F1)......................................10-5
10.1.10 IDE_TIM—IDE Timing Register (IDE—D31:F1)............................10-6
10.1.11 SLV_IDETIM—Slave (Drive 1) IDE Timing Register
(IDE—D31:F1)...............................................................................10-7
10.1.12 SDMA_CNT—Synchronous DMA Control Register
(IDE—D31:F1)...............................................................................10-8
10.1.13 SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)...............................................................................10-8
10.1.14 IDE_CONFIG—IDE I/O Configuration Register.............................10-9
10.2
Bus Master IDE I/O Registers (D31:F1) ...................................................10-11
10.2.1 BMIC[P,S]—Bus Master IDE Command Register .......................10-11
10.2.2 BMIS[P,S]—Bus Master IDE Status Register..............................10-12
10.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register .......................................................................................10-12
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