參數(shù)資料
型號(hào)： 80960JS
廠商： Intel Corp.
英文描述： High Performance 32-bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式微處理器3.3（3.3高性能32位嵌入式處理器）
文件頁(yè)數(shù)： 50/86頁(yè)
文件大?。?/td> 1257K
代理商： 80960JS
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
50
Datasheet
RELATIVE OUTPUT TIMINGS
T
LX
Address Valid to ALE/ALE# Inactive
For 3.3 V Data Input Signals
For 5.0 V Data Input Signals
ALE/ALE# Width
Address Hold from ALE/ALE# Inactive
DT/R# Valid to DEN# Active
0.5T
C
- 5
0.5T
C
- 8
ns
(9)
T
LXL
T
LXA
T
DXD
0.5T
C
- 7
ns
Equal Loading (9)
BOUNDARY SCAN TEST SIGNAL TIMINGS
T
BSF
TCK Frequency
0.5T
F
MHz
T
BSCH
TCK High Time
15
ns
Measured at 1.5 V
(1)
Measured at 1.5 V
(1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
T
BSCL
TCK Low Time
15
ns
T
BSCR
T
BSCF
T
BSIS1
T
BSIH1
T
BSOV1
T
BSOF1
T
BSOV2
T
BSOF2
T
BSIS2
TCK Rise Time
TCK Fall Time
Input Setup to TCK
—
TDI, TMS
Input Hold from TCK
—
TDI, TMS
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
Input Setup to TCK
—
All Inputs (Non-Test)
Input Hold from TCK
—
All Inputs (Non-
Test)
NOTE:
See Table 33 on page 50 for note definitions for this table.
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
6
3
3
3
3
4
30
30
30
30
(1,10)
(1,10)
(1,10)
(1,10)
T
BSIH2
6
ns
Table 33. Note Definitions for Table 32, 80960Jx AC Characteristics
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN frequency.
3. Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than I
OL
. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
and XINT[7:0]# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition
at a particular clock edge. For asynchronous operation, NMI# and XINT[7:0]# must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
particular clock edge.
8. ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.
9. Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK.
11.Worst-case T
condition occurs on I/O pins when pins transition from a floating high input to driving a low
output state. The Address/Data Bus pins encounter this condition between the last access of a read, and
the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at 50 pF
loads.
Table 32. 80960Jx AC Characteristics (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Unit
Notes
相關(guān)PDF資料
PDF描述
80960JC High Performance 32-Bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
80960KB Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點(diǎn)單元的嵌入式32位微處理器)
80960MC Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點(diǎn)單元和存儲(chǔ)器管理單元的嵌入式32位微處理器)
80960RM 80960RM I/O Processor(80960RM I/O 處理器)
80960RN 80960RN I/O Processor(80960RN I/O 處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80960JT 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR
80960KA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960KB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT
80960MC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
80960SA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
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