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80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
12
Datasheet
2.6
Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to
detect as many as seven different trace event types. Alternatively,
mark
and
fmark
instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.7
Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor
’
s
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.
Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated peripherals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.
2.8
Test Features
The 80960Jx incorporates numerous features that enhance the user
’
s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE
mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically
“
remove
”
itself from a circuit board. This allows for system-level testing in which a
remote tester
—
such as an in-circuit emulator
—
can exercise the processor system.
The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.
The JTAG Boundary Scan feature is an attractive alternative to conventional
“
bed-of-nails
”
testing.
It can examine connections that might otherwise be inaccessible to a test system.