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參數(shù)資料
| 型號： | 80960JS |
| 廠商： | Intel Corp. |
| 英文描述： | High Performance 32-bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器) |
| 中文描述： | 高性能32位嵌入式微處理器3.3（3.3高性能32位嵌入式處理器） |
| 文件頁數(shù)： | 19/86頁 |
| 文件大?。?/td> | 1257K |
| 代理商： | 80960JS |
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80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Datasheet
19
BE[3:0]#
O
R(1)
H(Z)
P(1)
BYTE ENABLES
select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
32-bit bus:
BE3# enables data on AD[31:24]
BE2# enables data on AD[23:16]
BE1# enables data on AD[15:8]
BE0# enables data on AD[7:0]
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD[15:8])
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Byte Low Enable (enables data on AD[7:0])
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
BE0# becomes Address Bit 0 (A0)
The processor asserts byte enables, byte high enable and byte low enable during
T
a
.
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last T
d
cycle.
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A[3:2] described above.
WIDTH/
HLTD[1:0]
O
R(0)
H(Z)
P(1)
WIDTH/HALTED
signals denote the physical memory attributes for a bus
transaction:
WIDTH/
HLTD1
WIDTH/
HLTD0
0
0
8 Bits Wide
0
1
16 Bits Wide
1
0
32 Bits Wide
1
1
Processor Halted
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
D/C#
O
R(X)
H(Z)
P(Q)
DATA/CODE
indicates that a bus access is a data access (1) or an instruction
access (0). D/C# has the same timing as W/R#.
0 = instruction access
1 = data access
W/R#
O
R(0)
H(Z)
P(Q)
WRITE/READ
specifies, during a
T
a
cycle, whether the operation is a write (1) or
read (0). It is latched on-chip and remains valid during T
d
cycles.
0 = read
1 = write
DT/R#
O
R(0)
H(Z)
P(Q)
DATA TRANSMIT / RECEIVE
indicates the direction of data transfer to and from the
address/data bus. It is low during T
a
and T
w
/T
d
cycles for a read; it is high during
T
a
and T
w
/T
d
cycles for a write. DT/R# never changes state when DEN# is asserted.
0 = receive
1 = transmit
Table 8. Pin Description
—
External Bus Signals (Sheet 2 of 4)
NAME
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 80960JC | High Performance 32-Bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器) |
| 80960KB | Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點單元的嵌入式32位微處理器) |
| 80960MC | Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點單元和存儲器管理單元的嵌入式32位微處理器) |
| 80960RM | 80960RM I/O Processor(80960RM I/O 處理器) |
| 80960RN | 80960RN I/O Processor(80960RN I/O 處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 80960JT | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR |
| 80960KA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR |
| 80960KB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT |
| 80960MC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |
| 80960SA | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
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