
Datasheet
3
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
Contents
1.0
2.0
Introduction
..................................................................................................................7
80960Jx Overview
......................................................................................................8
2.1
80960 Processor Core ........................................................................................10
2.2
Burst Bus.............................................................................................................10
2.3
Timer Unit............................................................................................................11
2.4
Priority Interrupt Controller..................................................................................11
2.5
Instruction Set Summary.....................................................................................11
2.6
Faults and Debugging.........................................................................................12
2.7
Low Power Operation..........................................................................................12
2.8
Test Features......................................................................................................12
2.9
Memory-Mapped Control Registers ....................................................................13
2.10
Data Types and Memory Addressing Modes......................................................13
Packaging Information
...........................................................................................15
3.1
Available Processors and Packages...................................................................15
3.2
Pin Descriptions ..................................................................................................17
3.2.1
Functional Pin Definitions.......................................................................17
3.2.2
80960Jx 132-Lead PGA Pinout..............................................................23
3.2.3
80960Jx 132-Lead PQFP Pinout............................................................27
3.2.4
80960Jx 196-Ball MPBGA Pinout ..........................................................30
3.3
Package Thermal Specifications.........................................................................35
3.4
Thermal Management Accessories.....................................................................40
3.4.1
Heatsinks................................................................................................40
Electrical Specifications
........................................................................................41
4.1
Absolute Maximum Ratings.................................................................................41
4.2
Operating Conditions...........................................................................................41
4.3
Connection Recommendations...........................................................................42
4.4
VCC5 Pin Requirements (VDIFF) .......................................................................42
4.5
VCCPLL Pin Requirements.................................................................................43
4.6
DC Specifications................................................................................................44
4.7
AC Specifications................................................................................................48
4.7.1
AC Test Conditions and Derating Curves ..............................................51
4.7.1.1 Ouput Delay or Hold vs. Load Capacitance ..............................51
4.7.1.2 T
LX
vs. AD Bus Load Capacitance............................................53
4.7.1.3 ICC Active vs. Frequency..........................................................55
4.7.2
AC Timing Waveforms ...........................................................................59
Bus Functional Waveforms
..................................................................................65
5.1
Basic Bus States.................................................................................................75
5.2
Boundary-Scan Register.....................................................................................76
Device Identification
...............................................................................................82
6.1
80960JS/JC/JT Device Identification Register....................................................83
6.2
80960JD Device Identification Register ..............................................................84
6.3
80960JA/JF Device Identification Register..........................................................85
Revision History
.......................................................................................................86
3.0
4.0
5.0
6.0
7.0