參數(shù)資料
型號(hào)： 80960JS
廠商： Intel Corp.
英文描述： High Performance 32-bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式微處理器3.3（3.3高性能32位嵌入式處理器）
文件頁(yè)數(shù)： 18/86頁(yè)
文件大小： 1257K
代理商： 80960JS
80960JA/JF/JD/JS/JC/JT 3.3 V Microprocessor
18
Datasheet
Table 8.
Pin Description
—
External Bus Signals (Sheet 1 of 4)
NAME
TYPE
DESCRIPTION
AD[31:0]
I/O
S(L)
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS
carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory. During an address (
T
a
) cycle, bits 31:2 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T
d
) cycle, read or write
data is present on one or more contiguous bytes, comprising AD[31:24], AD[23:16],
AD[15:8] and AD[7:0]. During write operations, unused pins are driven to
determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a
T
a
cycle, specifies the
number of data transfers during the bus transaction.
AD1
AD0
Bus Transfers
0
0
1 Transfer
0
1
2 Transfers
1
0
3 Transfers
1
1
4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
write
—
AD[31:2] are driven with the last data value on the AD bus.
read
—
AD[31:4] are driven with the last address value on the AD bus; AD[3:2]
are driven with the value of A[3:2] from the last data cycle.
Typically, AD[1:0] reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE
indicates the transfer of a physical address. ALE is
asserted during a
T
cycle and deasserted before the beginning of the T
d
state. It is
active HIGH and floats to a high impedance state during a hold cycle (T
h
).
ALE#
O
R(1)
H(Z)
P(1)
ADDRESS LATCH ENABLE
indicates the transfer of a physical address. ALE# is
the inverted version of ALE. This signal gives the 80960Jx a high degree of
compatibility with existing 80960Kx systems.
ADS#
O
R(1)
H(Z)
P(1)
ADDRESS STROBE
indicates a valid address and the start of a new bus access.
The processor asserts ADS# for the entire
T
cycle. External bus control logic
typically samples ADS# at the end of the cycle.
A[3:2]
O
R(X)
H(Z)
P(Q)
ADDRESS[3:2]
comprise a partial demultiplexed address bus.
32-bit memory accesses:
the processor asserts address bits A[3:2] during
T
a
. The
partial word address increments with each assertion of RDYRCV# during a burst.
16-bit memory accesses:
the processor asserts address bits A[3:1] during
T
a
with A1
driven on the BE1# pin. The partial short word address increments with each
assertion of RDYRCV# during a burst.
8-bit memory accesses:
the processor asserts address bits A[3:0] during
T
a
, with
A[1:0] driven on BE[1:0]#. The partial byte address increments with each assertion
of RDYRCV# during a burst.
相關(guān)PDF資料
PDF描述
80960JC High Performance 32-Bit Embedded 3.3V Microprocessor(3.3V高性能32位嵌入式處理器)
80960KB Embedded 32-Bit Microprocessor With Integrated Floating-Point Unit(帶有集成的浮點(diǎn)單元的嵌入式32位微處理器)
80960MC Embedded 32Bit Microprocessor With Integrated Floating_Point Unit And Memory Unit(帶有集成的浮點(diǎn)單元和存儲(chǔ)器管理單元的嵌入式32位微處理器)
80960RM 80960RM I/O Processor(80960RM I/O 處理器)
80960RN 80960RN I/O Processor(80960RN I/O 處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
80960JT 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3 V EMBEDDED 32-BIT MICROPROCESSOR
80960KA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR
80960KB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT
80960MC 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT
80960SA 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS
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