參數(shù)資料
型號: 7641
英文描述: 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述: 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù): 9/137頁
文件大小: 2145K
代理商: 7641
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 7641 group uses the standard 7600 series instruction set. Refer
to the 7600 Series Software Manual for details on the instruction set.
The 7600 series has an upward compatible instruction set, of which
instruction execution cycles are shortened, for 740 series.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is
0
, the high-order 8 bits becomes
00
16
. If the stack
page selection bit is
1
, the high-order 8 bits becomes
01
16
.
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PC
H
and PC
L
. It is used to indicate the address of the next in-
struction to be executed.
Fig. 6 7600 series CPU register structure
A
Accumulator
b7
b7
b7
b7
b0
b7
b8
b15
b0
b7
b0
b0
b0
b0
X
Index register X
Y
Index register Y
S
Stack pointer
PC
L
Program counter
PC
H
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
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