參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 41/137頁
文件大?。?/td> 2145K
代理商： 7641
40
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(1) Cycle Steal Transfer Mode
When the DMAC Channel x (x = 0, 1) Transfer Mode Selection Bit
(DxTMS) is set to
“
0
”
, the respective DMAC Channel x operates in
the cycle steal transfer mode.
When a request of the specified transfer factor is generated, the
selected channel transfers one byte of data from the address indi-
cated by the Source Register into the address indicated by the
Destination Register.
There are two kinds of DMA transfer triggers supported: hardware
transfer factor and software trigger. Hardware transfer factors can
be selected by the DMACx (x = 0, 1) Hardware Transfer Request
Factor Bit (DxHR). To only use the Interrupt Request Bit, the inter-
rupt can be disabled by setting its Interrupt Enable Bit of Interrupt
Control Register to
“
0
”
.
The DMA transfer request as a software trigger can be generated
by setting the DMA Channel x (x = 0, 1) Software Transfer Trigger
Bit (DxSWT) to
“
1
”
.
The Source Registers and Transfer Destination Registers can be
either decreased or increased by 1 after transfer completion by
setting bits 0 to 3 in the DMAC Channel x (x = 0, 1) Mode Regis-
ter. When the Transfer Count Register underflows, the Source
Registers and Destination Registers are reloaded from their
latches if the DMAC Register Reload Disable Bit (DRLDD) is
“
0
”
.
The Transfer Count Register value is reloaded after an underflow
regardless of DRLDD setting. At the same time, the DMAC Inter-
rupt Request Bit and the DMA Channel x (x = 0, 1) Count Register
Underflow Flag are set to
“
1
”
.
The DMAC Channel x Disable After Count Register Underflow En-
able Bit (DxDAUE) is
“
1
”
, the DMAC Channel x Enable Bit
(DxCEN) goes to
“
0
”
at an under flows of Transfer Count Register.
By setting the DMAC Channel x (x = 0, 1) Register Reload Bit
(DxRLD) to
“
1
”
, the Source Registers, Destination Registers, and
Transfer Count Registers can be updated to the values in their re-
spective latches.
When one signal among USB endpoint signals is selected as the
hardware transfer request factor, and DMAC Channel x (x = 0, 1)
USB and Master CPU Bus Interface Enable Bit (DxUMIE) is
“
1
”
;
transfer between the USB FIFO and the master CPU bus interface
input/output buffer can be performed effectively. This transfer
function is only valid in the cycle steal mode. To validate this func-
tion, the DMAC Channel x (x = 0, 1) USB and the Master CPU Bus
Interface Enable Bit (bit 5 of DxTR) must be set to
“
1
”
. The follow-
ing shows an example of a transfer using this function.
Packet Transfer from USB FIFO to Master
CPU Bus Interface Buffer
When the USB OUT_PKT_RDY is selected as the hardware trans-
fer request factor; if the USB OUT_PKT_RDY is
“
1
”
and the
master CPU bus interface output buffer is empty, the transfer re-
quest is generated and the transfer is initiated. The
OUT_PKT_RDY retains
“
1
”
and a transfer request is generated
each time the output buffer empties until all the data in the corre-
sponding endpoint FIFO has been transferred.
The transfer ends when the last byte in the USB receive packet is
transferred and the OUT_PKT_RDY flag goes to
“
0
”
(in the case
of AUTO_CLR bit =
“
1
”
).
Byte Transfer from USB FIFO to Master CPU
Bus Interface Buffer
When the USB Endpoint 1 OUT_FIFO_NOT_EMPTY is selected
as a hardware transfer request factor, if there is data in the USB
Endpoint 1 FIFO and the master CPU bus interface output buffer
is empty; a transfer request is generated and the transfer is initi-
ated. The transfer is performed by unit of one byte.
Transfer from Master CPU Bus Interface
Buffer to USB FIFO
When the USB Endpoint X (X = 1 to 4) IN_PKT_RDY
(IN_PKT_RDY =
“
0
”
) is selected as a hardware transfer request
factor, if there is data in the master CPU bus interface output
buffer and the data in the USB FIFO is within the specified packet
size, a transfer request is generated.
The DMA transfer is terminated when a command (A0 =
“
1
”
) is in-
put to the master CPU bus interface input buffer.
The timing chart for a cycle steal transfer caused by a hardware-
related transfer request and a software trigger are shown in Figure
33 and 34, respectively.
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