參數(shù)資料
型號(hào)： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 27/137頁
文件大小： 2145K
代理商： 7641
26
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts one of the internal clock
φ
divided by 8, 16, 32,
64.
G
TY
OUT
Output Function
In the timer mode, a signal of which polarity is inverted each time
the timer underflows is output from the CNTR
1
pin. This is enabled
by setting the Timer Y Output Control Bit to
“
1
”
.
When the CNTR
1
Active Edge Switch Bit is
“
0
”
, the CNTR
1
pin
starts pulses output beginning at
“
H
”
; when this bit is
“
1
”
, the
CNTR
1
pin starts pulses output beginning at
“
L
”
.
When using a timer in this mode, set the port P4
4
direction regis-
ter to output mode.
(2) Period Measurement Mode
CNTR
1
interrupt request is generated at a rising/falling edge of
CNTR
1
pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the aforementioned operation, the operation in period
measurement mode is the same as in timer mode. (The TY
OUT
output function is not usable.)
The timer value just before the reloading at rising/falling of CNTR
1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR
1
pin input signal is found by
CNTR
1
interrupt.
When the CNTR
1
Active Edge Switch Bit is
“
0
”
, the falling edge is
detected; when this bit is
“
1
”
, the rising edge is detected.
When using a timer in this mode, set the port P4
4
direction regis-
ter to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. (The TY
OUT
output function is not usable.)
When the CNTR
1
Active Edge Switch Bit is
“
0
”
, the rising edge is
counted; when this bit is
“
1
”
, the falling edge is counted.
When using a timer in this mode, set the port P4
4
direction regis-
ter to input mode.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
When using a timer in this mode, set the port P4
4
direction regis-
ter to input mode.
Fig. 21 Structure of timer Y mode register
I
Notes
G
Timer Y Write Control
If the Timer Y Write Control Bit is
“
1
”
, when the value is written in
the address of timer Y, the value is loaded only in the latch. The
value in the latch is loaded in timer Y after timer Y underflows.
If the Timer Y Write Control Bit is
“
0
”
, when the value is written in
the address of timer Y, the value is loaded in the timer Y and the
latch at the same time.
When the value is to be written in latch only, unexpected value
may be set in the high-order timer if the writing in high-order latch
and the underflow of timer Y are performed at the same timing.
G
CNTR
1
Interrupt Active Edge Selection
The CNTR
1
interrupt active edge depends on the selection of
CNTR
1
Active Edge Switch Bit.
However, in pulse width HL continuously measurement mode,
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
Active Edge Switch Bit.
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