參數(shù)資料
型號(hào)： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 33/137頁
文件大小： 2145K
代理商： 7641
32
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
UART1, UART2
The UART consists of two channels: UART1 and UART2. Each
has a dedicated timer provided to generate transfer clocks and op-
erates independently. Both UART1 and UART2 have the same
functions.
Twelve serial data transfer formats can be selected, and the trans-
fer formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
The transfer speed (baud rate) is expression as follows:
Transfer speed (baud rate) = fi / {(n + 1)
16 }
n: The contents of UARTx (x = 1, 2) baud rate generator
fi: Using UART clock prescaling select bits, select any one of
φ
,
φ
/
8,
φ
/32,
φ
/256, SCSGCLK, SCSGCLK/8, SCSGCLK/32 and
SCSGCLK/256
O
E
R
PER
FER
0034
16
003C
16
Receive buffer register 1
Receive buffer register 2
Receive shift register 1
Receive shift register 2
Address 0030
16
Address 0038
16
(
R
B
F
)
r
r
u
p
t
r
e
q
o
r
i
n
t
e
r
r
u
U
A
e
R
R
R
T
x
m
o
d
e
r
e
g
i
s
t
e
r
UARTx control register
A
A
d
d
d
r
r
e
e
s
s
s
s
0
0
0
0
3
3
3
1
B
1
6
6
d
R
c
c
c
e
e
e
i
i
i
v
v
v
e
e
e
b
b
s
u
u
u
f
f
m
f
f
e
e
m
r
r
f
f
i
u
u
n
l
l
l
l
f
i
e
l
n
a
t
r
g
e
r
e
e
u
p
e
t
s
r
e
t
q
(
u
U
x
s
R
t
B
(
F
U
)
x
g
e
E
S
)
SPdetector
UART character length select bits
S
T
d
e
t
e
c
t
o
r
7 bits
8
b
9 bits
i
t
s
P
R
8
5
/
X
D
2
/
U
R
S
X
C
D
1
L
K
P
8
1
/
U
P
X
8
4
/
D
2
/
U
S
T
R
X
D
1
D
P
8
0
/
U
T
Y
S
C
S
G
C
L
K
P
r
e
s
c
a
1
1/8
1/32
/
2
l
1
e
r
/
1
5
6
Baud rate generator
S
T
/
S
P
/
P
A
g
e
n
e
r
a
t
o
r
Clock control circuit
1
/
1
6
A
A
d
d
d
r
r
e
e
s
s
s
s
e
e
s
s
0
0
0
0
3
3
5
1
D
1
6
6
d
P
S
2
/
8
6
/
C
R
T
X
S
1
D
P
8
2
/
C
T
S
RTS control register
P8
7
/RTS
P8
3
/RTS
2
/STXD
Frequency
division ratio
1/(n+1)
A
A
d
d
d
r
r
e
e
s
s
A
A
s
s
e
e
s
s
e
r
e
0
0
0
0
s
s
3
3
s
s
6
1
E
1
e
s
e
s
6
6
0
0
d
d
d
d
r
0
0
3
3
1
1
9
1
6
6
d
Character length select bit
T
T
r
a
a
n
n
s
s
m
m
i
i
t
t
s
s
h
h
i
i
f
f
t
t
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
r
T
T
r
a
a
n
n
s
s
m
m
i
i
t
t
b
b
u
u
f
f
f
f
e
e
r
r
r
r
e
e
g
g
i
i
s
s
t
t
e
e
r
r
1
2
r
T
(
r
T
a
C
n
M
s
m
)
i
t
c
o
m
p
l
e
f
l
a
g
Transmit interrupt source select bit
Transmit interrupt
request (UxTX)
s
m
i
t
b
u
f
f
e
f
l
a
g
(
T
B
T
r
a
n
r
e
)
m
p
t
y
E
UART status register
Data bus
Data bus
φ
UART clock
prescaling select bits
U
s
A
e
R
e
T
c
c
b
l
i
o
t
c
k
l
t
0034
16
003C
16
A
A
d
d
d
r
r
e
e
s
s
s
s
e
e
s
s
0
0
0
0
3
3
5
1
D
1
6
6
d
Address 0032
16
Address 003A
16
Fig. 26 UARTx (x = 1, 2) block diagram
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