參數(shù)資料
型號(hào): 7641
英文描述: 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述: 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù): 77/137頁
文件大小: 2145K
代理商: 7641
76
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Slow Memory Wait
The 7641 Group is equipped with the slow memory wait function
(Software wait, RDY wait, and Extended RDY wait: software wait
plus RDY input anytime wait) for easier interfacing with external
devices that have long access times. The slow memory wait func-
tion can be enabled in the memory expansion mode and
microprocessor mode. The appropriate wait mode is selected by
setting bits 0 to 3 of CPU mode register B (address 0001
16
). This
function can extend the read cycle or write cycle only for access to
an external memory. However, this wait function cannot be en-
abled for access to addresses 0008
16
to 000F
16
.
(1) Software wait
The software wait is selected by setting
00
to the Slow Memory
Wait Mode Select Bits of CPU mode register B (address 0001
16
).
Read/write cycles (
L
width of RD pin/WR pin) can be extended
by one to three
φ
cycles. The number of cycles to be extended can
be selected with the Slow Memory Wait Select Bits. When the
software wait function is selected, the RDY pin status becomes in-
valid.
(2) RDY wait
RDY Wait is selected by setting
10
to the Slow Memory Wait
Mode Select Bits of CPU mode register B (address 0001
16
). When
a fixed time of
L
is input to the RDY pin at the beginning of a
read/write cycle (before
φ
cycle falls), the MCU goes to the RDY
state. The read/write cycle can then be extended by one to three
φ
cycles. The number of
φ
cycles to be added can be selected by
the Slow Memory Wait Bits.
(3) Software wait + Extended RDY wait
Extended RDY Wait is selected by setting
11
to the Slow
Memory Wait Mode Select Bits of CPU mode register B (address
0001
16
). The read/write cycle can be extended when a fixed time
of
L
is input to the RDY pin at the beginning of a read/write cycle
(before
φ
cycle falls). The RDY pin state is checked continually at
each fall of
φ
cycle until the RDY pin goes to
H
. When
H
is in-
put to the RDY pin, the wait is released within 1, 2, or 3
φ
cycles
(as selected with the Slow Memory Wait Bits).
Fig. 72 Software wait timing diagram
X
IN
φ
O
D
O
U
T
A
U
T
RD
W
R
C
P
M
B
=
0
0
1
6
C
P
M
B
=
0
1
1
6
1-cycle software wait
No wait
CPMB = 02
16
2-cycle software wait
C
P
M
B
=
0
3
1
6
3-cycle software wait
N
o
t
e
:
T
h
i
s
d
i
a
g
r
a
m
a
s
s
u
m
e
s
φ
=
X
I
N
/
2
.
Fig. 73 RDY wait timing diagram
X
IN
φ
OUT
AD
OUT
RD
WR
CPMB = 08
16
CPMB = 09
16
CPMB = 0A
16
CPMB = 0B
16
RDY
t
su
1-cycle RDY wait
No wait
2-cycle RDY wait
3-cycle RDY wait
t
su
t
su
t
su
t
su
t
su
Note
: This diagram assumes
φ
= X
IN
/2.
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