參數(shù)資料
型號： 7641
英文描述： 7641 Group Datasheet Datasheet 2145K/MAR.26.02
中文描述： 7641組數(shù)據(jù)表數(shù)據(jù)表2145K/MAR.26.02
文件頁數(shù)： 110/137頁
文件大?。?/td> 2145K
代理商： 7641
109
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Symbol
Table 27 Definition of each bit in status register (SRD)
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (70
16
)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF
16
) is input.
Also, the status register can be cleared by writing the clear status
register command (50
16
).
After reset, the status register is set to
“
80
16
”
.
Table 27 shows the status register. Each bit in this register is ex-
plained below.
Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to
“
0
”
(busy) during write or erase operation
and is set to
“
1
”
when these operations ends.
After power-on, the sequencer status is set to
“
1
”
(ready).
Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to
“
1
”
. When the erase status is
cleared, it is set to
“
0
”
.
Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to
“
1
”
.
The program status is set to
“
0
”
when it is cleared.
If
“
1
”
is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (50
16
) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to
“
1
”
.
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“
1
”
“
0
”
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Status name
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Busy
-
Terminated normally
Terminated normally
-
-
-
-
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